EL5225 datasheet(2/12 Pages) INTERSIL

2 / 12 page

FN7356.0

March 11, 2004

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are

at the specified temperature and are pulsed tests, therefore: TJ = TC = TA

Absolute Maximum Ratings (TA = 25°C)

Supply Voltage between VS & GND. . . . . . . . 4.5V (min) to 18V (max)

Supply Voltage between VSD & GND . . 3V (min) to VS and 7V (max)

Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves

Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Electrical Specifications

VS = 15V, VSD = 5V, VREFH = 13V, VREFL = 2V, RL = 1.5kΩ and CL = 200pF to 0V, TA = 25°C, unless

otherwise specified.

PARAMETER

DESCRIPTION

CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY

Supply Current

No load

11.5

ISD

Digital Supply Current

0.17

0.35

ANALOG

VOL

Output Swing Low

Sinking 5mA (VREFH = 15V, VREFL = 0)

150

VOH

Output Swing High

Sourcing 5mA (VREFH = 15V, VREFL = 0)

14.85

14.95

ISC

Short Circuit Current

RL = 10Ω

100

140

PSRR

Power Supply Rejection Ratio

VS+ is moved from 14V to 16V

Program to Out Delay

4ms

VAC

Accuracy referred to the ideal value

Code = 512

∆VMIS

Channel to Channel Mismatch

Code = 512

VDROOP

Droop Voltage

mV/ms

RINH

Input Resistance @ VREFH, VREFL

Ω

REG

Load Regulation

IOUT = 5mA step

0.5

1.5

mV/mA

CAP

Band Gap

Bypass with 0.1µF

1.3

1.6

DIGITAL

VIH

Logic 1 Input Voltage

VSD = 5V

VSD = 3.3V

FCLK

Clock Frequency

5MHz

VIL

Logic 0 Input Voltage

VSD = 3.3V/5V

Setup Time

Hold Time

tLC

Load to Clock Time

tCE

Clock to Load Line

tDCO

Clock to Out Delay Time

Negative edge of SCLK

RSDIN

SDIN Input Resistance

Ω

TPULSE

Minimum Pulse Width for EXT_OSC

Signal

5µs

Duty Cycle

Duty Cycle for EXT_OSC Signal

INL

Integral Nonlinearity Error

1.3

LSB

DNL

Differential Nonlinearity Error

0.5

LSB

F_OSC

Internal Refresh Oscillator Frequency

OSC_Select = 0

kHz

EL5225

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