STM32L4P5CE datasheet(147/310 Pages) STMICROELECTRONICS

147 / 310 page

Table 27. Current consumption in Run and Low-power run modes, code with data

processing running from Flash in dual bank, ART enable (Cache ON Prefetch OFF)

Symbol

Parameter

Conditions

fHCLK

TYP

MAX(1)

Unit

Voltage

scaling

25°C

55°C

85°C

105°C 125°C

25°C

55°C

85°C

105°C 125°C

IDD

(Run)

Supply

current in

Run mode

fHCLK = fHSE

up to 48MHz

included,

bypass mode

PLL ON above

48 MHz all

peripherals

disable

Range 2

26 MHz

3.30

3.65

4.65

6.10

8.75

TBD

16 MHz

2.10

2.45

3.45

4.90

7.50

TBD

8 MHz

1.20

1.50

2.50

3.95

6.55

TBD

4 MHz

0.71

1.05

2.05

3.45

6.05

TBD

2 MHz

0.47

0.80

1.80

3.20

5.80

TBD

1 MHz

0.36

0.68

1.65

3.10

5.65

TBD

100 KHz

0.25

0.58

1.55

2.95

5.55

TBD

Range 1

Boost Mode

120 MHz 16.00

16.50

18.00

20.00

23.50

TBD

Range 1

Normal

Mode

80 MHz

11.50

12.50

13.50

15.50

18.50

TBD

72 MHz

10.50

11.00

12.50

14.50

17.50

TBD

64 MHz

9.50

10.00

11.50

13.00

16.50

TBD

48 MHz

7.10

7.60

8.90

10.50

14.00

TBD

32 MHz

4.85

5.30

6.60

8.35

11.50

TBD

24 MHz

3.70

4.15

5.45

7.15

10.50

TBD

16 MHz

2.60

3.00

4.25

6.00

9.10

TBD

IDD

(LPRun)

Supply

current in

Low-power

run mode

fHCLK = fMSI

all peripherals disable

2 MHz

420

840

1950

3550

6350

TBD

µA

1 MHz

305

700

1800

3400

6200

TBD

400 KHz

225

610

1700

3300

6100

TBD

100 KHz

185

570

1700

3250

6050

TBD

1. Guaranteed by characterization results, unless otherwise specified.

STM32L4P5CE Datasheet(PDF) 147 Page - STMicroelectronics

STM32L4P5CE Datasheet(HTML) 147 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL