LPC47B34X datasheet(21/250 Pages) SMSC

21 / 250 page

SIGNAL NAME

TYPE

DESCRIPTION

SERIRQ

I/O

Serial IRQ.

PCI_CLK

Input

PCI Clock.

LPC Cycles

The following cycle types are supported by the LPC protocol.

CYCLE TYPE

TRANSFER SIZE

I/O Write

1 Byte Transfer

I/O Read

1 Byte Transfer

DMA Write

1 byte

DMA Read

1 byte

The LPC47B34x ignores cycles that it does not support.

Field Definitions

The data transfers are based on specific fields that are used in various combinations, depending on

the cycle type. These fields are driven onto the LAD[3:0] signal lines to communicate address, control

and data information over the LPC bus between the host and the LPC47B34x. See the Low Pin Count

(LPC) Interface Specification Reference, Section 4.2 for definition of these fields.

nLFRAME Usage

nLFRAME is used by the host to indicate the start of cycles and the termination of cycles due to an

abort or time-out condition. This signal is to be used by the LPC47B34x to know when to monitor the

bus for a cycle.

This signal is used as a general notification that the LAD[3:0] lines contain information relative to the

start or stop of a cycle, and that the LPC47B34x monitors the bus to determine whether the cycle is

intended for it. The use of nLFRAME allows the LPC47B34x to enter a lower power state internally.

There is no need for the LPC47B34x to monitor the bus when it is inactive, so it can decouple its state

machines from the bus, and internally gate its clocks.

When the LPC47B34x samples nLFRAME active, it immediately stops driving the LAD[3:0] signal

lines on the next clock and monitor the bus for new cycle information.

The nLFRAME signal functions as described in the Low Pin Count (LPC) Interface Specification

Reference.

I/O Read and Write Cycles

The LPC47B34x is the target for I/O cycles. I/O cycles are initiated by the host for register or FIFO

accesses, and will generally have minimal Sync times. The minimum number of wait-states between

bytes is 1. EPP cycles will depend on the speed of the external device, and may have much longer

Sync times.

Data transfers are assumed to be exactly 1-byte. If the CPU requested a 16 or 32-bit transfer, the

host will break it up into 8-bit transfers.

See the Low Pin Count (LPC) Interface Specification Reference, Section 5.2, for the sequence of

cycles for the I/O Read and Write cycles.

LPC47B34X Datasheet(PDF) 21 Page - SMSC Corporation

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