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LPC47B37X Datasheet(PDF) 21 Page - SMSC Corporation

Part # LPC47B37X
Description  100 Pin Enhanced Super I/O for LPC Bus with SMBus Controller for Commercial Applications
PDF  254 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

LPC47B37X Datasheet(HTML) 21 Page - SMSC Corporation

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21
FLOPPY DISK CONTROLLER
The Floppy Disk Controller (FDC) provides the
interface between a host microprocessor and the
floppy disk drives.
The FDC integrates the
functions of the Formatter/Controller, Digital Data
Separator, Write Precompensation and Data Rate
Selection logic for an IBM XT/AT compatible FDC.
The true CMOS 765B core guarantees 100% IBM
PC XT/AT compatibility in addition to providing
data overflow and underflow protection.
The FDC is compatible to the 82077AA using
SMSC's proprietary floppy disk controller core.
FDC Internal Registers
The Floppy Disk Controller contains eight internal
registers that facilitate the interfacing between the
host microprocessor and the disk drive. Table 2
shows the addresses required to access these
registers. Registers other than the ones shown
are not supported.
The rest of the description
assumes that the primary addresses have been
selected.
Table 2 - Status, Data and Control Registers
(Shown with base addresses of 3F0 and 370)
PRIMARY
ADDRESS
SECONDARY
ADDRESS
R/W
REGISTER
3F0
3F1
3F2
3F3
3F4
3F4
3F5
3F6
3F7
3F7
370
371
372
373
374
374
375
376
377
377
R
R
R/W
R/W
R
W
R/W
R
W
Status Register A (SRA)
Status Register B (SRB)
Digital Output Register (DOR)
Tape Drive Register (TDR)
Main Status Register (MSR)
Data Rate Select Register (DSR)
Data (FIFO)
Reserved
Digital Input Register (DIR)
Configuration Control Register (CCR)
Status Register A (SRA)
Address 3F0 READ ONLY
This register is read-only and monitors the state of the internal interrupt signal and several disk interface
pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the
PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F0.
PS/2 Mode
7
6
5
4
3
2
1
0
INT
PENDING
nDRV2
STEP
nTRK0 HDSEL nINDX
nWP
DIR
RESET
COND.
0
1
0
N/A
0
N/A
N/A
0
BIT 0 DIRECTION
Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a logic
"0" indicates outward direction.



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