LM5071 datasheet(13/18 Pages) NSC

13 / 18 page

Error Amplifier

An internal high gain error amplifier is provided within the

LM5071. The amplifier’s non-inverting reference is set to a

fixed reference voltage of 1.25V. The inverting input is con-

nected to the FB pin. In non-isolated applications, the power

converter output is connected to the FB pin via voltage

scaling resistors. Loop compensation components are con-

nected between the COMP and FB pins. For most isolated

applications the error amplifier function is implemented on

the secondary side of the converter and the internal error

amplifier is not used. The internal error amplifier is config-

ured as an open drain output and can be disabled by con-

necting the FB pin to ARTN. An internal 5K pull-up resistor

between a 5V reference and COMP can be used as the

pull-up for an optocoupler in isolated applications.

Current Limit / Current Sense

The LM5071 provides a cycle-by-cycle over current protec-

tion function. Current limit is accomplished by an internal

current sense comparator. If the voltage at the current sense

comparator input CS exceeds 0.5V with respect to RTN/

ARTN, the output pulse will be immediately terminated. A

small RC filter, located near the CS pin of the controller, is

recommended to filter noise from the current sense signal.

The CS input has an internal MOSFET which discharges the

CS pin capacitance at the conclusion of every cycle. The

discharge device remains on an additional 50ns after the

beginning of the new cycle to attenuate the leading edge

spike on the current sense signal.

The LM5071 current sense and PWM comparators are very

fast, and may respond to short duration noise pulses. Layout

considerations are critical for the current sense filter and

sense resistor. The capacitor associated with the CS filter

must be located very close to the device and connected

directly to the pins of the controller (CS and ARTN). If a

current sense transformer is used, both leads of the trans-

former secondary should be routed to the sense resistor and

the current sense filter network. A sense resistor located in

the source of the primary power MOSFET may be used for

current sensing, but a low inductance resistor is required.

When designing with a current sense resistor, all of the noise

sensitive low power ground connections should be con-

nected together local to the controller and a single connec-

tion should be made to the high current power return (sense

resistor ground point).

Oscillator, Shutdown and Sync

Capability

A single external resistor connected between the RT and

ARTN pins sets the LM5071 oscillator frequency. Internal to

the LM5071–50 device (50% duty cycle limited option) is an

oscillator divide by two circuit. This divide by two circuit

creates an exact 50% duty cycle clock which is used inter-

nally to create a precise 50% duty cycle limit function. Be-

cause of this divide by two, the internal oscillator actually

operates at twice the frequency of the output (OUT). For the

LM5071–80 device the oscillator frequency and the opera-

tional output frequency are the same. To set a desired output

operational frequency (F), the RT resistor can be calculated

from:

LM5071-80:

LM5071-50:

The LM5071 can also be synchronized to an external clock.

The external clock must have a higher frequency than the

free running oscillator frequency set by the RT resistor. The

clock signal should be capacitively coupled into the RT pin

with a 100pF capacitor. A peak voltage level greater than 3.7

volts at the RT pin is required for detection of the sync pulse.

The sync pulse width should be set between 15 to 150ns by

the external components. The RT resistor is always required,

whether the oscillator is free running or externally synchro-

nized. The voltage at the RT pin is internally regulated to a 2

volts. The RT resistor should be located very close to the

device and connected directly to the pins of the controller

(RT and ARTN).

PWM Comparator / Slope

Compensation

The PWM comparator compares the current ramp signal

with the loop error voltage derived from the error amplifier

output. The error amplifier output voltage at the COMP pin is

offset by 1.4V and then further attenuated by a 3:1 resistor

divider. The PWM comparator polarity is such that 0 Volts on

the COMP pin will result in zero duty cycle at the controller

output. For duty cycles greater than 50 percent, current

mode control circuits are subject to sub-harmonic oscillation.

By adding an additional fixed slope voltage ramp signal

(slope compensation) to the current sense signal, this oscil-

lation can be avoided. The LM5071-80 integrates this slope

compensation by summing a current ramp generated by the

oscillator with the current sense signal. Additional slope

compensation may be added by increasing the source im-

pedance of the current sense signal (with an external resis-

tor between the CS pin and current sense resistor). Since

the LM5071-50 is not capable of duty cycles greater than

50%, there is no slope compensation feature in this device.

Softstart

The softstart feature allows the power converter to gradually

reach the initial steady state operating point, thereby reduc-

ing start-up stresses, output overshoot and current surges.

At power on, after the V

CC undervoltage lockout threshold is

satisfied, an internal 10µA current source charges an exter-

nal capacitor connected to the SS pin. The capacitor voltage

will ramp up slowly and will limit the COMP pin voltage and

the duty cycle of the output pulses.

Gate Driver and Maximum Duty

Cycle Limit

The LM5071 provides an internal gate driver (OUT), which

can source and sink a peak current of 800mA. The LM5071

is available in two duty cycle limit options. The maximum

output duty cycle is typically 80% for the LM5071-80 option

and precisely equal to 50% for the LM5071-50 option. The

maximum duty cycle function for the LM5071-50 is accom-

LM5071 Datasheet(PDF) 13 Page - National Semiconductor (TI)

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