156

Timing Waveforms

The address information is latched in the on-chip registers

on the falling edge of E (T = 0). Minimum address set up and

hold time requirements must be met. After the required hold

time, the addresses may change state without affecting

device operation. During time (T = 1) the output becomes

enabled but data is not valid until during time (T = 2). W must

remain high throughout the read cycle. After the output data

has been read, E may return high (T = 3). This will disable

the output buffer and all inputs, and ready the RAM for the

next memory cycle (T = 4).

(8)

(7) TAVEL

(6)

(4) TEHQZ

HIGH Z

VALID DATA OUT

(6)

HIGH Z

TAVEL

(7)

-1

TIME

01

2

3

4

5

REFERENCE

(2) TAVQV

(17) TELEL

TELAX

NEXT ADD

TEHEL

(2) TAVQY

TEHEL

(5) TELEH

(1) TELQV

(3) TELQX

DQ

W

E

A

FIGURE 1. READ CYCLE

VALID ADD

TRUTH TABLE

TIME

REFERENCE

INPUTS

DATA I/O

DQ

FUNCTION

E

W

A

-1

H

X

X

Z

Memory Disabled

0

H

V

Z

Cycle Begins, Addresses are Latched

1

L

H

X

X

Output Enabled

2

L

H

X

V

Output Valid

3

H

X

V

Read Accomplished

4

H

X

X

Z

Prepare for Next Cycle (Same as -1)

5

H

V

Z

Cycle Ends, Next Cycle Begins (Same as 0)

HM-6514/883