6

TH7834C

1997A–IMAGE–05/02

Operating

Precautions

Shorting the video outputs to VSS or VDD, even temporarily, can permanently damage

the output amplifiers.

Operating Conditions (T = 25°C)

Note:

If no exposure time control is required,

Φ

Typical current in V

Timing Diagram

Figure 3. Line Timing Diagram

•

Minimum exposure time: Ti min = readout time.

For data rate of 5 MHz: Ti min =

= 608.6 µs.

Note:

It is better to clean the shift registers (with running clocks) and not to stop clocking them

after readout time.

Table 1. DC Characteristics

Parameter

Symbol

Value

Unit

Min.

Typ.

Max.

Output Amplifier Drain Supply

V

14.5

15

15.5

V

Substrate Voltage

V

SS

00

V

Reset DC Bias

V

V

V

Output Amplifier Source Bias

V

0V

Output Gate DC Bias

V

2.2

2.4

2.6

V

Photosensitive Zone DC Bias

V

ST

3.544.5

V

Antiblooming Diode Bias

VA

14

14.5

15

V

ΦP3-4

ΦP1-2

ΦΦ

LS1-2,

LS3-4

ΦΦ

R1-2,

R3-4

ΦEc1

(clamp)

External

ΦEch

(Sampling)

Detailed timing diagram

for transfert from

photosite to register

(see fig. 4)

Detailed pixel

timing diagram

(see fig. 5)

ΦΦ

L1,

L2

Readout time for line M

Cleaning

Pixel N

Integration time Ti for line M+1

3043

5MHz

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