TLE8110ED datasheet(42/74 Pages) INFINEON

42 / 74 page

Data Sheet

Rev. 1.0

2018-03-07

TLE8110ED

Smart Multichannel Low Side Switch with Parallel Control and SPI Interface

Control of the device

This chapter describes the SPI-Interface signals, the protocol, registers and commands. Reading this chapter

allows the Software Engineer to control the device. The chapter contains also some information about

communication safety features of the protocol.

12.1

Internal Clock

The device contains an internal clock oscillator.

12.2

SPI Interface. Signals and Protocol

12.2.1

Description 16 bit SPI Interface Signals

S_CS - Chip Select:

The system micro controller selects the TLE8110ED by means of the S_CS pin. Whenever the pin is in low state,

data transfer can take place. When S_CS is in high state, any signals at the S_CLK and S_SI pins are ignored

and S_SO is forced into a high impedance state.

S_CS High to Low transition:

• The information to be transferred loaded into the shift register (16-bit Protocol).

S_CS Low to High transition:

• Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3...) of eight

S_CLK signals have been detected. (See Modulo-8 Counter: Chapter 12.2.4.2).

S_CLK - Serial Clock:

This input pin clocks the internal shift register. The serial input (S_SI) transfers data is shifted into register on

the falling edge of S_CLK while the serial output (S_SO) shifts the information out on the rising edge of the

serial clock. It is essential that the S_CLK pin is in low state whenever chip select CS makes any transition.

S_SI - Serial Input:

Serial input data bits are shifted in at this pin, the most significant bit first. The bit at the S_SI Pin is read on the

falling edge of S_CLK.

S_SO Serial Output:

Data is shifted out serially at this pin, the most significant bit first. S_SO is in high impedance state until the

S_CS pin goes to low state. The next bits will appear at the S_SO is in high impedance state until the S_CS goes

to low state. The next bits will appear at the S_SO pin following the rising edge of S_CLK.

Table 14

Electrical Characteristics: Internal Clock

3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current

flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Unit

Note or

Test Condition

Number

Min.

Typ.

Max.

Parallel Inputs

internal clock oscillator frequency fint_osc

500

kHz

1) Parameter not subject to production test. Specified by design.

TLE8110ED Datasheet(PDF) 42 Page - Infineon Technologies AG

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