TLE75242-ESH datasheet(39/83 Pages) INFINEON

39 / 83 page

Datasheet

Rev. 1.0

2017-11-23

TLE75242-ESH

SPIDER+ 12V

Power Stages

For each PWM generator 4 parameters can be set:

• duty cycle (bits PWM_CR0.DC for PWM Generator 0)

– 8 bits are available to achieve 0.39% duty cycle resolution

– when the micro-controller programs a new duty cycle, the PWM generator waits until the previous cycle

is completed before using the new duty cycle (this happens also when the duty cycle is either 0% or

100% - the new duty cycle is taken with the next PWM cycle)

– the maximum duty cycle achievable is 99.61% (PWM_CR0.DC set to “11111111B”). It is possible to

achieve 100% by setting PWM_CR0.FREQ to “11B”

•frequency (bits PWM_CR0.FREQ for PWM Generator 0)

– with 2 bits is possible to select the divider for fINT to achieve the needed duty cycle

–00B = fINT / 1024 (when fINT = 102.4 kHz the corresponding PWM frequency is 100 Hz)

–01B = fINT / 512 (corresponding to 200 Hz)

–10B = fINT / 256 (corresponding to 400 Hz)

• channel output control and mapping registers PWM_OUT and PWM_MAP)

– any channel can be mapped to each PWM Generator

– together with 2 parallel input it is possible to have 4 independent PWM groups of channels with low

effort from the point of view of micro-controller resources and SPI data traffic

Figure 21 expands the concept shown in Figure 10 adding the PWM Generators.

TLE75242-ESH Datasheet(PDF) 39 Page - Infineon Technologies AG