USB3317C_V01 datasheet(39/76 Pages) SMSC

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Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 26MHz Reference Clock

Datasheet

SMSC USB3317 REV C

Revision 2.1 (06-02-10)

DATASHEET

6.2.2

ULPI Register Read

A ULPI register read operation is given in Figure 6.5. The Link drives a TXD CMD byte with DATA[7:6]

= 11h for a register read. DATA[5:0] of the ULPI TXD command bye contain the register address.

At T0, the Link will place the TXD CMD on the data bus. At T2, the PHY will bring NXT high, signaling

that the Link it is ready to accept the data transfer. At T3, the PHY reads the TXD CMD, determines

it is a register read, and asserts DIR to gain control of the bus. The PHY will also de-assert NXT. At

T4, the bus ownership has transferred back to the PHY and the PHY drives the requested register

onto the data bus. At T5, the Link will read the data bus and the PHY will drop DIR low returning control

of the bus back to the Link. After the turn around cycle, the Link must drive a ULPI Idle command at T6.

A ULPI extended register read operation is shown in Figure 6.6.To read an extended register, the Link

writes the TX CMD with the address set to 2Fh. At T2, the PHY will assert NXT, signaling the Link it

is ready to accept the extended address. At T3, the Link places the extended register address on the

bus. At T4, the PHY reads the extended address, and asserts DIR to gain control of the bus. The PHY

will also de-assert NXT. At T5, the bus ownership has transferred back to the PHY and the PHY drives

the requested register onto the data bus. At T6, the Link will read the data bus and the PHY will de-

assert DIR returning control of the bus back to the Link. After the turn around cycle, the Link must

drive a ULPI Idle command at T6.

Figure 6.5 ULPI Register Read in Synchronous Mode

DIR

CLK

DATA[7:0]

STP

NXT

Txd Cmd Reg

Read

Idle

Reg Data

Turn around

Idle

USB3317C Datasheet(PDF) 39 Page - SMSC Corporation