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AS7C331MNTD18A Datasheet(PDF) 1 Page - Alliance Semiconductor Corporation

Part # AS7C331MNTD18A
Description  3.3V 1M x 18 Pipelined SRAM with NTD
PDF  18 Pages
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Manufacturer  ALSC [Alliance Semiconductor Corporation]
Direct Link  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS7C331MNTD18A Datasheet(HTML) 1 Page - Alliance Semiconductor Corporation

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December 2004
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C331MNTD18A
12/24/04, v 2.7
Alliance Semiconductor
P. 1 of 18
3.3V 1M x 18 Pipelined SRAM with NTDTM
Features
• Organization: 1,048,576 words × 18 bits
•NTD™ architecture for efficient bus operation
• Fast clock speeds to 166 MHz
• Fast clock to data access: 3.4/3.8 ns
•Fast OE access time: 3.4/3.8 ns
• Fully synchronous operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic block diagram
Selection guide
-166
-133
Units
Minimum cycle time
6
7.5
ns
Maximum clock frequency
166
133
MHz
Maximum clock access time
3.4
3.8
ns
Maximum operating current
290
270
mA
Maximum standby current
90
80
mA
Maximum CMOS standby current (DC)
60
60
mA
Address
D
Q
CLK
register
Output
register
DQ [a,b]
20
20
CLK
CE0
CE1
CE2
A[19:0]
OE
CLK
CEN
Control
CLK
logic
Data
D
Q
CLK
input
register
18
18
OE
1M x 18
SRAM
array
R/W
DQ [a,b]
BWa
BWb
CLK
Q
D
ADV / LD
LBO
burst logic
addr. registers
Write delay
20
ZZ
CLK
18
18
18
18


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