LP4068-01

Jan.-2019

www.lowpowersemi.com

Page 2 of 8

Preliminary Datasheet

LP4068

Functional Pin Description

Package Type

LP4068B6F

LP4068QVF

Pin

Configurations

1

3

5

4

CHRG

ISET

TOP VIEW

2

GND

BAT

VIN

VIN

FULL

CHRG

BAT

ISET

NC

1

2

3

EN 4

8

7

6

5 GND

TOP VIEW

Pin Description

NAME

Pin

DESCRIPTION

SOT23-5

TDFN-8

CHRG

1

3

Open-Drain Charge Status Output. When the battery is charging, the

CHRG pin is pulled low by an internal NMOS. When the charge cycle

is completed, the pin could be pulled High by an external pull high

resistor.

GND

2

5

GND is the connection to system ground.

BAT

3

8

BAT is the connection to the battery. Typically a 10µF Tantalum

capacitor is needed for stability when there is no battery attached.

When a battery is attached, only a 1uF ceramic capacitor is required.

VIN

4

1

VIN is the input power source. Connect to a wall adapter.

ISET

5

7

Charge Current Program. The charge current is programmed by

FULL

2

Open-Drain Charge Status Output. When the battery is charging, the FULL

pin could be pulled High by an external pull high resistor. When the charge

cycle is completed, the pin is pulled Low by an internal N-channel MOSFET.

EN

4

Charge Enable Input (active low).

NC

6

No Connector.