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LP140WD2 Datasheet(PDF) 9 Page - LG Semicon Co.,Ltd. |
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LP140WD2 Datasheet(HTML) 9 Page - LG Semicon Co.,Ltd. |
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9 / 28 page  Product Specification LP140WD2 Liquid Crystal Display Ver. 1.0 Dec. 16. 2010 9 / 28 Description Symbol Min Max Unit Notes LVDS Clock to Data Skew Margin t SKEW - 400 + 400 ps 85MHz > Fclk ≥ 65MHz t SKEW - 600 + 600 ps 65MHz > Fclk ≥ 25MHz LVDS Clock to Clock Skew Margin (Even to Odd) t SKEW_EO - 1/7 + 1/7 T clk - Maximum deviation of input clock frequency during SSC F DEV - ± 3 % - Maximum modulation frequency of input clock during SSC F MOD - 200 KHz - Description Symb ol Min Max Unit Notes LVDS Differential Voltage |V ID| 100 600 mV - LVDS Common mode Voltage V CM 0.6 1.8 V - LVDS Input Voltage Range V IN 0.3 2.1 V - 3-3-1. DC Specification 3-3-2. AC Specification LVDS + LVDS - 0V VCM # |VID| = |(LVDS+) – (LVDS-)| # VCM = {(LVDS+) + (LVDS-)}/2 |VID| VIN_MAX VIN_MIN 3-3. LVDS Signal Timing Specifications LVDS Data tSKEW LVDS Clock Tclk tSKEW (Fclk = 1/Tclk) 1) 85MHz > Fclk ≥ 65MHz : -400 ~ +400 2) 65MHz > Fclk ≥ 25MHz : -600 ~ +600 |
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