AS7C31025B

3/24/04, v. 1.3

Alliance Semiconductor

P. 2 of 9

®

Functional description

The AS7C31025B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 x 8

bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.

high-performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems.

When CE is high the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data

on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention,

A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives I/O pins

with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output

drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The AS7C31025B is packaged in common

industry standard packages.

Absolute maximum ratings

NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-

tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect reliability.

Truth table

Key: X = don’t care, L = low, H = high.

Parameter

Symbol

Min

Max

Unit

–0.50

+5.0

V

Voltage on any pin relative to GND

–0.50

V

Power dissipation

–1.0

W

Storage temperature (plastic)

–65

+150

–55

+125

DC current into outputs (low)

–20

mA

CE

WE

OE

Data

Mode

H

X

X

High Z

L

H

H

High Z

LHL

LL

X