IS25LP064A-RHLA2 datasheet(76/99 Pages) ISSI

76 / 99 page

IS25LP064A/032A

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

11/06/2015

Figure 8.59 FRQDTR Sequence (with command decode cycles)

CE #

SCK

Instruction = EDh

CE #

SCK

3-byte Address

High Impedance

...

Mode 3

Mode 0

20 16 12

5 1

21 17 13

Data

Out

4 0

IO0

IO1

IO0

22 18 14

23 19 15

8 4

9 5

10 6

11 7

3 Dummy Cycles

IO2

IO3

IO1

IO2

IO3

6 2

7 3

5 1

4 0

6 2

7 3

5 1

4 0

6 2

7 3

5 1

4 0

6 2

7 3

5 1

4 0

6 2

7 3

5 1

4 0

6 2

7 3

5 1

4 0

6 2

7 3

5 1

4 0

6 2

7 3

5 1

4 0

6 2

7 3

5 1

4 0

6 2

7 3

5 1

4 0

6 2

7 3

5 1

4 0

6 2

7 3

Data

Out

Data

Out

Data

Out

Data

Out

Data

Out

Data

Out

Data

Out

Data

Out

Data

Out

Data

Out

Data

Out

5 1

4 0

6 2

7 3

Mode Bits

...

5 1

4 0

6 2

7 3

Data

Out

Notes:

1. If the mode bits=AXh (

where X is don’t care), it can execute the AX read mode (without command). When the

mode bits are different from AXh, the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.10 Read Dummy Cycles.

3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bit cycles

are same, then X should be Hi-Z.

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