PIC16F913 datasheet(95/272 Pages) MICROCHIP

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Preliminary

DS41250E-page 93

PIC16F917/916/914/913

8.0

COMPARATOR MODULE

The

comparator

module

contains

two

analog

comparators. The inputs to the comparators are

multiplexed with I/O port pins RA<3:0>, while the outputs

are multiplexed to pins RA<5:4>. An on-chip Comparator

Voltage Reference (CVREF) can also be applied to the

inputs of the comparators.

The CMCON0 register (Register 8-1) controls the

comparator input and output multiplexers. A block

diagram of the various comparator configurations is

shown in Figure 8-3.

CMCON0 – COMPARATOR CONFIGURATION REGISTER (ADDRESS: 9Ch)

R-0

R/W-0

C2OUT

C1OUT

C2INV

C1INV

CIS

CM2

CM1

CM0

bit 7

bit 0

bit 7

C2OUT: Comparator 2 Output bit

When C2INV = 0:

=C2 VIN+ > C2 VIN-

=C2 VIN+ < C2 VIN-

When C2INV = 1:

=C2 VIN+ > C2 VIN-

=C2 VIN+ < C2 VIN-

bit 6

C1OUT: Comparator 1 Output bit

When C1INV = 0:

=C1 VIN+ > C1 VIN-

=C1 VIN+ < C1 VIN-

When C1INV = 1:

=C1 VIN+ > C1 VIN-

=C1 VIN+ < C1 VIN-

bit 5

C2INV: Comparator 2 Output Inversion bit

= C2 Output inverted

= C2 Output not inverted

bit 4

C1INV: Comparator 1 Output Inversion bit

= C1 Output inverted

= C1 Output not inverted

bit 3

CIS: Comparator Input Switch bit

When CM<2:0> = 010:

=C1 VIN- connects to RA3/AN3/C1+/VREF+/SEG15

C2 VIN- connects to RA2/AN2/C2+/VREF-/COM2

=C1 VIN- connects to RA0/AN0/C1-/SEG12

C2 VIN- connects to RA1/AN1/C2-/SEG7

When CM<2:0> = 001:

=C1 VIN- connects to RA3/AN3/C1+/VREF+/SEG15

=C1 VIN- connects to RA0/AN0/C1-/SEG12

When CM<2:0> = 101:

=C2 VIN+ connects to internal 0.6V reference

=C2 VIN+ connects to RA2/AN2/C2+/VREF-/COM2

bit 2-0

CM<2:0>: Comparator Mode bits(1)

See Figure 8-3 for comparator modes and CM<2:0> bit settings.

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry,

weak pull-ups, and interrupt-on-change if available. The corresponding TRIS bit

must be set to Input mode in order to allow external control of the voltage on the pin.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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