SE050 datasheet(21/30 Pages) NXP

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NXP Semiconductors

SE050

Plug & Trust Secure Element

SE050

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Product data sheet

Rev. 3.0 — 12 May 2020

504930

21 / 30

aaa-037451

70 % level

Vhigh

tCLKW

CLK (et al)

Vlow

0.5 VDD

1/fCLK

tfCLK

tfRST

tfIO

trCLK

trRST

trIO

30 % level

1) During AC testing the inputs RST_N, I2C_SDA, I2C_SCL are driven at 0 V to +0.3 V for a LOW

input level and at VCC -0.3 V to VCC for a HIGH input level. Clock period and signal pulse (duty

cycle) timing is measured at 50 % of VCC.

2) tr is defined as rise time between 30 % and 70 % of the signal amplitude. tf is defined as fall

time between 70 % and 30 % of the signal amplitude.

Figure 10. External clock drive and AC test timing reference points of I2C_SDA, I2C_SCL,

and RST_N (see 1) and 2)) in open-drain mode

Table 15. Electrical AC characteristics of IO1, IO2, CLK and RST_N (ISO7816 interface)

Conditions: VCC = 1.8 V ± 10 % or 3 V ± 10 % V; VSS = 0 V; Tamb = -40 °C to +105 °C, unless otherwise specified. Typical

values are only referenced for information. They are subject to change without notice.

Symb

Parameter

Conditions

Min

Typ

Max

Unit

Input/Output: IO1/IO2

[1]

[2]

μs

trIO

I/O Input rise time

Input/reception mode

[3]

[2]

0.25 x

tIOWx_min

μs

tfIO

I/O Input fall time

Input/reception mode

[1]

[2]

μs

[3]

[2]

0.25 x

tIOWx_min

μs

trOIO

I/O Output rise time

Output/transmission mode; CL

= 30 pF

[2]

0.1

μs

tfOIO

I/O Output fall time

Output/transmission mode; CL

= 30 pF

[2]

0.1

μs

Inputs: CLK and RST_N

fCLK

External clock frequency

in ISO/IEC 7816 UART

applications

tCLKW, tamb and VCC in their

specified limits

[4]

0.85

11.5

MHz

tCLKW

Clock pulse width i.r.t. clock

period (positive pulse duty

cycle of CLK)

trCLK

CLK input rise time

[5]

[6]

tfCLK

CLK input fall time

[2]

[6]

trRST

RST_N input rise time

[2]

400

μs

tfRST

RST_N input fall time

[2]

[7]

400

μs

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