STM32F722IC datasheet(177/229 Pages) STMICROELECTRONICS

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DS11853 Rev 6

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STM32F722xx STM32F723xx

Electrical characteristics

201

CAN (controller area network) interface

Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate

function characteristics (CANx_TX and CANx_RX).

6.3.30

FMC characteristics

Unless otherwise specified, the parameters given in Table 93 to Table 106 for the FMC

interface are derived from tests performed under the ambient temperature, fHCLK frequency

and VDD supply voltage conditions summarized in Table 16, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 11

•

Measurement points are done at CMOS levels: 0.5VDD

Refer to Section 6.3.20: I/O port characteristics for more details on the input/output

characteristics.

Asynchronous waveforms and timings

Figure 62 through Figure 65 represent asynchronous waveforms and Table 93 through

Table 100 provide the corresponding timings. The results shown in these tables are

obtained with the following FMC configuration:

•

AddressSetupTime = 0x1

•

AddressHoldTime = 0x1

•

DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)

•

BusTurnAroundDuration = 0x0

•

Capcitive load CL = 30 pF

In all timing tables, the THCLK is the HCLK clock period

Table 92. USB FS PHY BCD electrical characteristics

Symbol

Parameter

Conditions

Min Typ Max

Unit

IDDUSB

Primary detection mode consumption

300

µA

Secondary detection mode consumption

300

RDAT_LKG

Data line leakage resistance

300

VDAT_LKG

Data line leakage voltage

0.0

3.6

RDCP_DAT

Dedicated charging port resistance across D+/D-

200

VLGC_HI

Logic high

2.0

3.6

VLGC_LOW

Logic low

0.8

VLGC

Logic threshold

0.8

2.0

VDAT_REF

Data detect voltage

0.25

3.6

VDP_SRC

D+ source voltage

0.5

3.6

VDM_SRC

D- source voltage

0.5

3.6

IDM_SINK

D- sink current

175

µA

IDP_SINK

D+ sink current

175

IDP_SRC

Data contact detect current source

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