STM32F722IC datasheet(24/229 Pages) STMICROELECTRONICS

24 / 229 page

Functional overview

STM32F722xx STM32F723xx

24/229

DS11853 Rev 6

3.6

AXI-AHB bus matrix

The STM32F722xx and STM32F723xx system architecture is based on 2 sub-systems:

•

An AXI to multi AHB bridge converting AXI4 protocol to AHB-Lite protocol:

–

3x AXI to 32-bit AHB bridges connected to AHB bus matrix

–

1x AXI to 64-bit AHB bridge connected to the embedded Flash memory

•

A multi-AHB Bus-Matrix

–

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, USB

HS) and the slaves (Flash memory, RAM, FMC, Quad-SPI, AHB and APB

peripherals) and ensures a seamless and efficient operation even when several

high-speed peripherals work simultaneously.

Figure 7. STM32F722xx and STM32F723xx AXI-AHB bus matrix architecture(1)

1. The above figure has large wires for 64-bits bus and thin wires for 32-bits bus.

MSv41005V1

Arm Cortex-M7

32-bit Bus Matrix - S

FLASH

512KB

SRAM1

176KB

SRAM2

16KB

AHB

periph2

FMC external

MemCtl

Quad-SPI

AXI to

multi-AHB

AHB

Periph1

DTCM RAM

ITCM RAM

16KB

64KB

64-bit AHB

64-bit BuS Matrix

ITCM

APB1

APB2

I/D Cache

8KB

DMA1

DMA2

USB OTG

STM32F722IC Datasheet(PDF) 24 Page - STMicroelectronics

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