August 2004

ASM4SSTVF16857

rev 2.0

DDR 14-Bit Registered Buffer

8 of 16

Timing Requirements

(Over recommended operating free-air temperature range, unless otherwise noted).

Guaranteed by design. Not 100% production tested.

* this parameter is not necessarily production tested.

Unit

Symbol

Parameters

Min

Max

Min

Max

Clock frequency

200

270

MHz

Pulse duration, CK, CKLB high or low

2.5

2.5

ns

Differential inputs active time

22

22

ns

Differential inputs inactive time

22

22

ns

Setup time, fast slew rate

0.75

0.4

Setup time, slow slew rate

Data before CLK, CLKB

0.9

0.6

ns

ns

Hold time, fast slew rate

0.75

0.4

Hold time, slow slew rate

Data after CLK, CLKB

0.9

0.6

ns

ns

Output slew rate, measurement point at 20% and 80%

1

4

1

4

V/ns

Note:

2. Data and clock inputs must be held at valid levels (not floating) for a minimum time of tINACTmax after which RESETB is taken low.

3. For data signal input slew rate >=V/ns

4. For data signal input slew rate >=0.5 V/ns and < 1V/ns

5. CLK,CLKB signals input slew rates are >=1V/ns