ASM5I9658 datasheet(6/14 Pages) ALSC

6 / 14 page

July 2005

ASM5I9658

rev 0.2

3.3V 1:10 LVCMOS PLL Clock Generator

6 of 14

Notice: The information in this document is subject to change without notice.

Table 6: AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 0°C to 70°C)1

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

fREF

Input reference frequency

÷2 feedback

PLL mode, external feedback

÷4 feedback

Input reference frequency in PLL bypass mode

100

250

125

250

MHz

PLL locked

fVCO

VCO operating frequency range

200

500

MHz

fMAX

Output Frequency

÷2 feedback

÷4 feedback

100

250

125

MHz

PLL locked

VPP

Peak-to-peak input voltage

PCLK

500

1000

LVPECL

VCMR

Common Mode Range

PCLK

1.2

VCC-0.9

LEPVCL

tPW,MIN

Input Reference Pulse Width

t(Ø)

Propagation Delay (static phase offset)

8 PCLK to

FB_IN

fREF=100MHz

any frequency

-70

-125

+80

+125

PLL locked

tPD

Propagation Delay PLL and divider bypass,

PCLK to Q0-9

1.0

4.0

tsk(O)

Output-to-output Skew

120

Output duty cycle

(T÷2)-

400

T÷2

(T÷2)+4

tR ,tF

Output Rise/Fall Time

0.1

1.0

0.55 to 2.4V

tPLZ, HZ

Output Disable Time

7.0

tPZL, LZ

Output Enable Time

6.0

tJIT(CC)

Cycle-to-cycle jitter

tJIT(PER)

Period Jitter

tJIT(Ø)

I/O Phase Jitter

fVCO=500 MHz and ÷ 2 feedback, RMS (1σ)

fVCO=500 MHz and ÷ 4 feedback, RMS (1σ)

5.5

6.5

PLL closed loop bandwidth

12 

÷2 feedback

PLL mode, external feedback

÷4 feedback

6-20

2 - 8

MHz

tLOCK

Maximum PLL Lock Time

Note:1. AC characteristics apply for parallel output termination of 50Ω to VTT.

2. ÷2 PLL feedback (high frequency range) requires VCO_SEL=0, PLL_EN=1, BYPASS=1 and MR/OE=0.

3.÷4 PLL feedback (low frequency range) requires VCO_SEL=1, PLL_EN=1, BYPASS=1 and MR/OE=0.

4.In bypass mode, the ASM3P9658 divides the input reference clock.

5.The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO ÷ FB.

6.VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR

range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(Ø).

7.Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN . fREF. 100% and DCREF,MAX = 100% - DCREF,MIN.

8.Valid for fREF=50 MHz and FB=÷8 (VCO_SEL=1). For other reference frequencies: t(Ø) [pS] = 50 pS ± (1÷(120 . fREF)).

9.See application section for part-to-part skew calculation in PLL zero-delay mode.

10.Output duty cycle is DC = (0.5 ± 400 pS. fOUT) V 100%. E.g. the DC range at fOUT=100MHz is 46%<DC<54%. T = output period.

11.See application section for a jitter calculation for other confidence factors than 1 and a characteristic for other VCO frequencies.

12.-3 dB point of PLL transfer characteristics.

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