conversion, it is necessary to clock in the data indicating the

input that is selected for the conversion after the current one.

See Tables 1, 2 and Table 3.

If CS and SCLK go low simultaneously, it is the following

rising edge of SCLK that is considered the first rising edge

for clocking data into DIN.

There are no power-up delays or dummy conversions re-

quired with the ADC082S101. The ADC is able to sample

and convert an input to full conversion immediately following

power up. The first conversion result after power-up will be

that of IN1.

TABLE 1. Control Register Bits

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DONTC

DONTC

ADD2

ADD1

ADD0

DONTC

DONTC

DONTC

TABLE 2. Control Register Bit Descriptions

Bit #:

Symbol:

Description

7-6,2-0

DONTC

Don’t care. The value of these bits do not affect the device.

3

ADD0

These bits determine which input channel will be sampled and converted in

the next track/hold cycle. The mapping between codes and channels is

shown in Table 3.

4

ADD1

5

ADD2

TABLE 3. Input Channel Selection

ADD2

ADD1

ADD0

Input Channel

x

0

0

IN1 (Default)

x

0

1

IN2

x

1

x

Not allowed. The output signal at the D

OUT

pin is indeterminate if ADD1 is high.

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