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ADP1032ACPZ-5-R7 Datasheet(PDF) 5 Page - Analog Devices |
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ADP1032ACPZ-5-R7 Datasheet(HTML) 5 Page - Analog Devices |
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5 / 37 page  Data Sheet ADP1032 Rev. 0 | Page 5 of 37 Parameter Symbol Min Typ Max Unit Test Conditions/Comments BUCK REGULATOR Output Voltage VOUT2 5.15 V ADP1032ACPZ-1 5.0 V ADP1032ACPZ-2 and ADP1032ACPZ-4 3.3 V ADP1032ACPZ-3 and ADP1032ACPZ-5 Output Voltage Accuracy −1.5 +1.5 % IOUT2 = 10 mA, applies to all models Load Regulation (ΔVOUT2/VOUT2)/ ΔIOUT2 −0.0005 %/mA IOUT2 = 2 mA to 50 mA Line Regulation (ΔVOUT2/VOUT2)/ ΔVOUT1 0.0004 %/V VOUT1 = 6 V to 28 V, IOUT2 = 7 mA Power FET On Resistance RON_NFET (BUCK) 1 Ω SW2 current (ISW2) = 100 mA RON_PFET (BUCK) 2.5 Ω ISW2 = 100 mA Current-Limit Threshold ILIM (BUCK) 280 300 320 mA SW2 Leakage Current P Type Metal-Oxide Semiconductor (PMOS) 0.03 0.5 µA VSW2 = 0 V N Type Metal-Oxide Semiconductor (NMOS) 0.03 0.5 µA VSW2 = 28 V Switching Frequency fSW (BUCK) 117.5 125 132.5 kHz SYNC = low or high fSYNC/4 kHz SYNC = external clock Minimum On Time 200 ns Soft Start Timer tSS (BUCK) 8 ms Active Pull-Down Resistor RPD (BUCK) 1.7 kΩ 1.23 V < VOUT1 < 4.5 V ISOLATORS, DC SPECIFICATIONS MCK, MSS, MO, SO, MGPI1, MGPI2, SGPI3 Input Threshold Logic High VIH 0.7 × VxVDD2 V Logic Low VIL 0.3 × VxVDD2 V Input Current II −1 +1 µA 0 V ≤ VINPUT ≤ VxVDD2 SCK, SSS, SI, MI Output Voltage Logic High VOH VxVDD2 − 0.1 V IOx3 = −20 µA, VIx = VIXH4 VxVDD2 − 0.4 V IOx3 = −2 mA, VIx = VIXH4 Logic Low VOL 0.1 V IOx3 = 20 µA, VIx = VIXL5 0.15 0.4 V IOx3 = 2 mA, VIx = VIXL5 SGPO1, SGPO2, MGPO3 Output Voltage Logic High VOH VxVDD2 − 0.1 V IOx3 = −20 µA, VIx = VIXH4 VxVDD2 − 0.4 V IOx3 = −500 µA, VIx = VIXH4 Logic Low VOL 0.1 V IOx3 = 20 µA, VIx = VIXL5 0.15 0.4 V IOx3 = 500 µA, VIx = VIXL5 SCK, SI, MI Tristate Leakage −1 +0.01 +1 µA MSS = logic high −1 +0.01 +1 µA VOX6 = VxVDD2 ISOLATORS, SWITCHING SPECIFICATION MCK, MSS, MO, SO SPI Clock Rate SPIMCK 16.6 MHz Latency (MSS) 100 125 ns Delay from MSS going low to the first data out is valid Input Pulse Width tPW 17 ns Within PWD limit Input Pulse Width Distortion tPWD 0.25 6.5 ns |tPLH − tPHL| |
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