SC1112TSTR datasheet(15/21 Pages) SEMTECH

15 / 21 page

 2001 Semtech Corp.

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POWER MANAGEMENT

SC1112

Theory Of Operation

The SC1112 was designed for the latest high speed mother

boards requiring a controled power up sequencing of the

Outputs, and a programable delay for the Power good sig-

nal.

Three Linear controllers have been incorperated into the

SC1112. The VTT output can be programmed to either a

1.250V or a 1.500V by applying a LOW or a HIGH control

signal to the VTTSEL pin. AGP output can also be

prgorammed via AGPSEL pin to a 1.50V or a 3.30V. The

SC1112 also provides an Adjustable output which utilizes

a resistive voltage divider.

The +5VSTBY supply will power the internal Reference,

Charge Pump, Oscillator, and the .et controllers. After the

+5VSTBy has been established, LDO outputs will track the

VTTIN (3.30V) supply as it is applied.

An external capaitor connected to the Delay pin will pro-

gram the VTT short circuit delay time (SC

td), and the PWRGD

delay time (PG

td).

During power up, an internal short circuit glitch timer will

start once the VTT Input Voltage exceeds the VTTIN

TH (1.5V).

During the glitch timer immunity time, determined by the

Delay capacitor (Delay time is approximately equal to

(Cdelay*SCTH)/ISC), the short circuit protection is disabled

to allow VTT output to rise above the trip threashold (0.7V).

If the VTT output has not risen above the trip threashold

after the immunity time has elapsed, the VTT output is

latched off and will only be enabled again if either the VTT

input voltage or the 5VSTBY is cycled.

PWRGD pin is kept low during the power up, until the VTT

output has reached its PG

td1.25 or PGtd1.5 level. At that time

the PWRGD source current I

PG (20uA) is enabled and will

start charging the external PWRGD delay capacitor

connected to the DELAY pin. Once the capacitor is charged

above the PG

Delay_TH (1.5V), the PWRGD pin is released from

ground. A detailed timing diagram is shown on pages 4 to

Also included is an overcurrent protection circuit that moni-

tors the VTT voltage. If the output voltage drops below

700mV, as would occur during an overcurrent or short

condition, the device will pull the drive pin low and latch

off the output.

.ixed Output Voltage Options (VTT, AGP)

Please refer to the Application Circuit on Page 1. The VTT

and the AGP fixed output voltage can be programed from

a Control logic signal. Table below shows the possible Volt-

ages:

Once the VTTSEL or the AGPSEL signal is established, an

internal resistive divider is used to compare the bandgap

reference voltage with the feed back output voltage. The

drive

voltage

then

adjusted

maintain the output voltage set by the internal resistor

divider. Referring to the block diagram on page 7.

It is possible to adjust the output voltage of the VTT or

AGP, by applying an external resistor divider to the sense

pin (please refer to .igure 1 on Page 11). Since the sense

pin sinks a nominal 100µA, the resistor

values should be selected to allow 10mA to flow through

the divider. This will ensure that variations in this current

do not adversely affect output voltage regulation. Thus a

target value for R2 (maximum) can be calculated:

Ω

≤

)

FIXED

(

OUT

The output voltage can only be adjusted upwards from the

fixed output voltage, and can be calculated using the

following equation:

Volts

100

)

FIXED

(

OUT

)

ADJUSTED

(

OUT

•











 +

•

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