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INA592ID Datasheet(PDF) 32 Page - Texas Instruments |
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INA592ID Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 44 page ![]() 10.2 Layout Example 12 k 6 k 2 3 1 6 5 -IN +IN Vout IN IN 1 Vout V V 2 Vref = GND 1 F 1 F V- V+ 7 4 12 k 6 k RL R1 R2 R3 R4 C1 Place bypass capacitors as close to IC as possible 1 REF 8 NC 2 ±IN 7 V+ 3 +IN 6 OUT 4 V± 5 SENSE INA592 ±IN +IN Low-impedance connection for reference terminal +V GND RL -V GND C1 C2 C2 Use ground pours for shielding the input signal pairs GND SENSE OUT REF Vout Figure 10-1. Example Schematic and Associated PCB Layout INA592 SBOS914D – OCTOBER 2018 – REVISED DECEMBER 2020 www.ti.com 32 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: INA592 |
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