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SPEAR-09-H022 Datasheet(PDF) 39 Page - STMicroelectronics

Part # SPEAR-09-H022
Description  SPEAr Head ARM 926, 200K customizable eASIC gates, large IP portfolio SoC
PDF  55 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPEAR-09-H022 Datasheet(HTML) 39 Page - STMicroelectronics

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SPEAR-09-H022
6 IP Description
39/55
6.8
USB 2.0 DEVICE
6.8.1
OVERVIEW
Three blocks drive the USB 2.0 Device interface on SPEAr Head.
The first one is the USB2.0PHY, which executes the serialization and the de-serialization and
implements the transceiver for the USB line.
The second is the UDC (USB 2.0 Device Controller). It is connected on AHB Bus and
generates the commands for USB2.0PHY in UTMI+ interface.
The last block is the USB Plug Detect, which detects the connection of the device.
6.8.1.1 USB2.0PHY
The USB2.0PHY is a hard macro designed using standard cells and custom cells. In this way is
possible to reach the max speed HS of USB: 480 Mbits/Sec.
6.8.1.2 UDC
The UDC is able to detect the USB connection speed via UTMI+ interface.
There is an AHB master and three slaves.
The UDC contains 6 endpoints (0 control, 1 Bulk IN, 2 Bulk OUT, 3 ISO IN, 4 ISO OUT, 5
Interrupt IN) and 4 configurations.
6.9
ETHERNET MAC 110
The Ethernet Media Access Controller (MAC 110) incorporates the requirements for operation
of an Ethernet / IEEE 802.3 compliant node and provides interface between the host system
and the Media Independent Interface (which is embedded in SPEAr Head).
MAC 110 core features are:
●
It can operate either in 100 Mbps mode or 10 Mbps mode, depending on the clock
provided on the MII interface
●
It can operate both in Half-Duplex mode and Full-Duplex mode.
When operating in the Half-Duplex mode, the MAC110 core is fully compliant to Section 4
of ISO / IEC 8802-3 (ANSI / IEEE Standard) and ANSI / IEEE 802.3.
When operating in the Full-Duplex mode, the MAC110 core is compliant to the IEEE
802.3x standard for Full-Duplex operations. It is also compatible with Home PNA 1.1.
The MAC110 core provides programmable enhanced features designed to minimize host
supervision, bus utilization, and pre- or post-message processing. These features include:
●
Ability to disable retires after a collision
●
Dynamic FCS generation on a frame-by-frame basis
●
Automatic Pad field insertion and deletion to enforce minimum frame size attributes
●
Automatic retransmission and detection of collision frames.
The MAC110 core can sustain transmission or reception of Minimal-Sized Back-To-Back
packets at full line speed with an Inter-Packet Gap (IPG) of 90.6 µs for 10 Mb/s and 0.96 µs for
100 Mb/s.



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