R7FA2L1AB2DFN datasheet(50/110 Pages) RENESAS

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Table 2.31

SCI timing (3)

Conditions: VCC = AVCC0 = 2.7 to 5.5 V

Parameter

Symbol

Min

Max

Unit

Test conditions

Simple IIC

(Standard mode)

SDA input rise time

tSr

—

1000

Figure 2.27

SDA input fall time

tSf

—

300

SDA input spike pulse removal time

tSP

4 × tIICcyc*1

Data input setup time

tSDAS

250

—

Data input hold time

tSDAH

—

SCL, SDA capacitive load

Cb*2

—

400

Simple IIC (Fast

mode)

SDA input rise time

tSr

—

300

Figure 2.27

SDA input fall time

tSf

—

300

SDA input spike pulse removal time

tSP

4 × tIICcyc*1

Data input setup time

tSDAS

100

—

Data input hold time

tSDAH

—

SCL, SDA capacitive load

Cb*2

—

400

Note 1. tIICcyc: Clock cycle selected by the SMR.CKS[1:0] bits.

Note 2. Cb indicates the total capacity of the bus line.

SDAn

SCLn

VIH

VIL

P*1

S*1

tSf

tSr

tSDAH

tSDAS

tSP

P*1

Test conditions:

VIH = VCC × 0.7, VIL = VCC × 0.3

VOL = 0.6 V, IOL = 6 mA

Sr*1

Note:

n = 0 to 3, 9

Note 1. S, P, and Sr indicate the following conditions:

S: Start condition

P: Stop condition

Sr: Restart condition

Figure 2.27

SCI simple IIC mode timing

RA2L1 Datasheet

2. Electrical Characteristics

R01DS0385EJ0100 Rev.1.00

Aug 06, 2020

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