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STM32L552CC Datasheet(PDF) 336 Page - STMicroelectronics

Part # STM32L552CC
Description  Ultra-low-power Arm® Cortex®-M33 32-bit MCUTrustZone®FPU, 165 DMIPS, up to 512 KB Flash memory, 256 KB SRAM, SMPS
PDF  340 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L552CC Datasheet(HTML) 336 Page - STMicroelectronics

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Revision history
STM32L552xx
336/340
DS12737 Rev 6
18-Dec-2019
2
(continued)
Updated Table 48: Current consumption in Run mode,
code with data processing running from SRAM2 and
power supplied by internal SMPS step down converter.
Updated Table 61: Current consumption in Sleep mode,
Flash ON and power supplied by internal SMPS step
down converter.
Updated Table 76: Current consumption in Stop 2 mode.
Updated Table 77: Current consumption in Stop 1
mode..
Updated Table 79: Current consumption in Standby
mode.
Updated Table 80: Current consumption in Shutdown
mode.
Updated Table 81: Current consumption in VBAT mode.
Updated Table 83: Low-power mode wakeup timings.
Updated Table 102: I/O static characteristics.
Updated Table 103: Output voltage characteristics.
Updated Table 129: SPI characteristics.
Updated Table 130: SAI characteristics.
Updated Table 146: OCTOSPI characteristics in SDR
mode.
Updated Table 147: OCTOSPI characteristics in DTR
mode (no DQS).
Updated Table 148: OCTOSPI characteristics in DTR
mode (with DQS)/Octal and HyperBus.
11-Feb-2020
3
Updated LQFP silhouette on cover page.
Updated Table 2: STM32L552xx features and peripheral
counts.
Updated Figure 1: STM32L552xx block diagram.
Updated Section 3.1: Arm® Cortex®-M33 core with
TrustZone® and FPU
Updated Section 3.2: Art Accelerator – instruction cache
(ICACHE)
Updated Section 3.6: Boot modes
Updated Table 5: Boot space versus RDP protection.
Updated Table 6: Example of memory map security
attribution vs SAU configuration regions.
Updated Table 7: Securable peripherals by TZSC.
Updated Section 3.9.4: SMPS step down converter.
Updated Table 10: STM32L552xx modes overview.
Updated Table 11: Functionalities depending on the
working mode.
Updated Table 12: STM32L552xx peripherals
interconnect matrix.
Updated Section 3.17.1: Nested vectored interrupt
controller (NVIC).
Table 164. Document revision history
Date
Revision
Changes



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