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STM32L552VCU6PTR Datasheet(PDF) 54 Page - STMicroelectronics |
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STM32L552VCU6PTR Datasheet(HTML) 54 Page - STMicroelectronics |
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54 / 340 page  Functional overview STM32L552xx 54/340 DS12737 Rev 6 3.14 Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, SDMMC1) and the slaves (Flash memory, RAM, FMC, OCTOSPI, AHB and APB peripherals). It also ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. Figure 8. Multi-AHB bus matrix MSv61198V1 CORTEX ®-M33 with TrustZone and FPU DMA1 DMA2 SDMMC1 BusMatrix-S 8 KB I-Cache MPCBB1 MPCBB2 MPCWM1 MPCWM2 MPCWM3 OctoSPI1 AHB2 peripherals AHB1 peripherals SRAM2 SRAM1 FLASH 512 KB FSMC MPCBBx: Memory protection controller block based Bus multiplexer Legend Master Interface Slave Interface MPCWMx: Memory protection controller Watermark |
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