STM32L552CCT3PTR datasheet(192/340 Pages) STMICROELECTRONICS

192 / 340 page

Table 72. Current consumption in Run mode, code with data processing running from Flash,

ICACHE on (1-way) and power supplied by external SMPS

Symbol

Parameter

Conditions(1)

TYP

Single

Bank

mode

TYP

Single

Bank

mode

Unit

TYP

Single

Bank

mode

TYP

Single

Bank

mode

Unit

VDD12

fHCLK

code

25°C

IDD(Run)

Supply

current in

Run mode

fHCLK = fHSE up to

48MHz included, bypass

mode PLL ON above 48

MHz all peripherals

disabled

VDD12=1.00V

fHCLK=26MHz

Reduced code

1.16

44.62

µA/MHz

Coremark

1.22

46.92

Dhrystone2.1

1.31

1.3

50.38

Fibonacci

1.11

42.69

While(1)

1.02

39.23

VDD12=1.10V

fHCLK=26MHz

Reduced code

1.41

54.23

µA/MHz

Coremark

1.48

56.92

Dhrystone2.1

1.58

60.77

Fibonacci

1.34

51.54

While(1)

1.24

47.69

fHCLK=80MHz

Reduced code

3.97

49.63

µA/MHz

Coremark

4.16

Dhrystone2.1

4.47

4.45

55.88

55.63

Fibonacci

3.73

46.63

While(1)

3.49

43.63

VDD12=1.20V fHCLK=110MHz

Reduced code

6.47

58.82

µA/MHz

Coremark

6.81

61.91

Dhrystone2.1

7.28

7.25

66.18

65.91

Fibonacci

6.09

55.36

While(1)

5.71

5.7

51.91

51.82

1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency =

85%.

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