STM32L552CCT3PTR datasheet(304/340 Pages) STMICROELECTRONICS

304 / 340 page

Electrical characteristics

STM32L552xx

304/340

DS12737 Rev 6

Delay block

Unless otherwise specified, the parameters given in Table 149 for delay block are derived

from tests performed under the ambient temperature, fPCLKx frequency and VDD supply

voltage conditions summarized in Table 27: General operating conditions with the

configuration shown in the figure below.

5.3.32

SD/SDIO/MMC card host interfaces (SDMMC)

Unless otherwise specified, the parameters given in Table 150 and Table 151 for SDIO are

derived from tests performed under the ambient temperature, fPCLKx frequency and VDD

supply voltage conditions summarized in Table 27: General operating conditions with the

following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 11

•

Capacitive load C = 30 pF

•

Measurement points are done at CMOS levels: 0.5VDD

Refer to Section 5.3.15: I/O port characteristics for more details on the input/output

characteristics.

Table 149. Dynamics characteristics: delay block characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tinit

Initial delay

1175

1375

1450

t∆

Unit delay

250

500

750

Table 150. Dynamics characteristics: SD / eMMC characteristics,

VDD=2.7V to 3.6 V(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fPP

Clock frequency in data transfer

mode

-0

MHz

SDIO_CK/fPCLK2 frequency ratio

8/3

tW(CKL)

Clock low time

fpp =52MHz

8.5

9.5

tW(CKH)

Clock high time

fpp =52MHz

8.5

9.5

CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(2)/DDR(2) mode

tISU

Input setup time HS

2.5

tIHD

Input hold time HS

CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(2)/DDR(2) mode

tOV

Output valid time HS

tOH

Output hold time HS

4.5

CMD, D inputs (referenced to CK) in SD default mode

tISUD

Input setup time SD

2.5

tIHD

Input hold time SD

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