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STM32L552CCT3PTR Datasheet(PDF) 335 Page - STMicroelectronics |
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STM32L552CCT3PTR Datasheet(HTML) 335 Page - STMicroelectronics |
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335 / 340 page  DS12737 Rev 6 335/340 STM32L552xx Revision history 339 8 Revision history Table 164. Document revision history Date Revision Changes 04-Oct-2019 1 Internal release 18-Dec-2019 2 Updated Section : Features. Updated Section 3.3: Memory protection unit. Updated Section 3.4: Embedded Flash memory. Updated Table 5: Boot space versus RDP protection. Updated Section 3.9.4: SMPS step down converter. Updated Table 11: Functionalities depending on the working mode. Updated Figure 7: STM32L552xx clock tree. Updated Table 27: General operating conditions. Updated Table 36: Current consumption in Run mode, code with data processing running from Flash in single bank, ICACHE ON in 2-way and power supplied by internal SMPS step down converter. Updated Table 37: Current consumption in Run mode, code with data processing running from Flash in single bank, ICACHE ON in 1-way and power supplied by internal SMPS step down converter. Updated Table 38: Current consumption in Run mode, code with data processing running from Flash in single bank, ICACHE disabled and power supplied by internal SMPS step down converter. Updated Table 42: Current consumption in Run mode, code with data processing running from Flash in dual bank, ICACHE ON in 2-way and power supplied by internal SMPS step down converter. Updated Table 43: Current consumption in Run mode, code with data processing running from Flash in dual bank, ICACHE ON in 1-way and power supplied by internal SMPS step down converter. Updated Table 44: Current consumption in Run mode, code with data processing running from Flash in dual bank, ICACHE disabled and power supplied by internal SMPS step down converter. Updated Table 46: Current consumption in Run mode, code with data processing running from SRAM1 and power supplied by internal SMPS step down converter. Updated Table 47: Current consumption in Run and Low-power run modes, code with data processing running from SRAM2. |
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