STM32L562VEI3PXXX datasheet(67/342 Pages) STMICROELECTRONICS

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DS12736 Rev 4

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STM32L562xx

Functional overview

3.28

True random number generator (RNG)

The RNG is a true random number generator that provides full entropy outputs to the

application as 32-bit samples. It is composed of a live entropy source (analog) and an

internal conditioning component.

The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct a

non-deterministic random bit generator (NDRBG).

The true random number generator:

•

delivers 32-bit true random numbers, produced by an analog entropy source

conditioned by a NIST SP800-90B approved conditioning stage,

•

can be used as entropy source to construct a non-deterministic random bit generator

(NDRBG),

•

produces four 32-bit random samples every 412 AHB clock cycles if fAHB < 77 MHz

(256 RNG clock cycles otherwise),

•

embeds start-up and NIST SP800-90B approved continuous health tests (repetition

count and adaptive proportion tests), associated with specific error management,

•

can be disabled to reduce power consumption, or enabled with an automatic low-power

mode (default configuration),

•

has an AMBA AHB slave peripheral, accessible through 32-bit word single accesses

only (else an AHB bus error is generated, and the write accesses are ignored).

3.29

Advanced encryption standard hardware accelerator (AES)

The devices embed an AES hardware accelerator that can be used both to encipher and to

decipher data using an AES algorithm.

The AES peripheral supports:

•

Encryption/decryption using AES Rijndael block cipher algorithm

•

NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm

•

128-bit and 256-bit register for storing the encryption, decryption or derivation key (4x

32-bit registers)

•

Electronic codebook (ECB), cipher block chaining (CBC), Counter mode (CTR), Galois

Counter Mode (GCM), Galois Message Authentication Code mode (GMAC) and Cipher

Message Authentication Code mode (CMAC) supported

•

Key scheduler

•

Key derivation for decryption

•

128-bit data block processing

•

128-bit, 256-bit key length

•

1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer

•

One 128-bit Register for the initialization vector when AES is configured in CBC mode

or for the 32-bit counter initialization when CTR mode is selected, GCM mode or

CMAC mode

•

Automatic data flow control with support of direct memory access (DMA) using 2

channels, one for incoming data, and one for out coming data

•

Suspend a message if another message with a higher priority needs to be processed.

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