AM29DL164D datasheet(51/57 Pages) AMD

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DS42515

AC CHARACTERISTICS

SRAM Write Cycle

Notes:

1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing.

2. t

CW is measured from CE1#s going low to the end of write.

3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.

4. t

AS is measured from the address valid to the beginning of write.

5. A write occurs during the overlap (t

WP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A

write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write

to the end of write.

Figure 30.

SRAM Write Cycle—WE# Control

Parameter

Symbol

Description

Min

Max

Unit

Write Cycle Time

Chip Enable to End of Write

Address Setup Time

Address Valid to End of Write

UB#s, LB#s to End of Write

Write Pulse Time

Write Recovery Time

WHZ

Write to Output High-Z

Data to Write Time Overlap

Data Hold from Write Time

End Write to Output Low-Z

Address

CS1#s

Data Undefined

UB#s, LB#s

WE#

Data In

Data Out

tWC

tCW

(See Note 1)

tAW

High-Z

Data Valid

CS2s

tCW

(See Note 1)

tBW

tWP

(See Note 4)

tAS

(See Note 3)

tWR (See Note 2)

tBW

tDW

tDH

tOW

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