| Electronic Components Datasheet Search |
|
ZMOD4450AI1R Datasheet(PDF) 13 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
ZMOD4450AI1R Datasheet(HTML) 13 Page - Renesas Technology Corp |
|
13 / 18 page ![]() ZMOD4450 Datasheet © 2019 Integrated Device Technology, Inc. 13 October 30, 2019 Figure 6. Bus Timing Table 9. Bus Timing Characteristics Parameter Symbol Standard Mode Fast Mode Units Maximum SCL clock frequency fSCL 100 400 kHz Minimum START condition hold time relative to SCL edge tHDSTA 4 µs Minimum SCL clock LOW width tLOW 4.7 µs Minimum SCL clock HIGH width tHIGH 4 µs Minimum START condition setup time relative to SCL edge tSUSTA 4.7 µs Minimum data hold time on SDA relative to SCL edge tHDDAT 0 µs Minimum data setup time on SDA relative to SCL edge tSUDAT 0.1 0.1 µs Minimum STOP condition setup time on SCL tSUSTO 4 µs Minimum bus free time between stop condition and start condition tBUS 4.7 µs SDA SCL tHDSTA tLOW tHDDAT tSUDAT tHIGH tSUSTA tHDSTA tSUSTO tBUS |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |