GS9021 datasheet(13/26 Pages) GENNUM

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the CRC values to correctly reflect the newly modified data.

To prevent the output EDH chip from indicating erroneous

CRC errors on each field, the GS9021 has two special

modes of operation, CRC_MODE and FLAG_MAP MODE.

3.10.1 CRC_MODE

In CRC_MODE, the CRC values in the EDH packet are

updated by the chip but the error flags are preserved and

unaltered, unless they are overwritten via the HOSTIF or the

FLAG PORT. This mode should be used by the output EDH

chip to prevent the newly processed data from creating

misleading EDH errors due to CRC mismatches. The

CRC_MODE pin takes precedence over the R/T pin in the

GS9021 with respect to the handling of the EDH flags. Thus

when CRC_MODE is HIGH, no flags are set or altered

(unless overwritten by the flags or HOSTIF port) regardless

of the state of the R/T pin. See Table 2 for the effect of the

different settings of R/T and CRC_MODE. The device is

placed in CRC_MODE by asserting the CRC_MODE pin

HIGH.

CRC_MODE is applicable when the processing circuitry

does not corrupt the EDH packet, as illustrated in Figure 6a.

In this configuration, the input EDH chip operates in normal

mode while the output EDH chip is in CRC_MODE. In this

scenario, the input IC receives the EDH packet and does

normal EDH processing. The output IC updates the EDH

packet with new CRC values but passes the EDH flags

through unaltered. Because of this, erroneous EDH flag

handling by the second GS9021 is not performed.

3.10.2 FLAG_MAP Mode

In FLAG_MAP mode, the FLAG PORT is used to read EDH

flags from the GS9021 and write them to another EDH chip.

To enable FLAG_MAP mode, the FLAG_MAP mode pin and

the F_R/W pin must be asserted HIGH (set F_R/W at least

one cycle ahead of FLAG_MAP). After a delay of tFEN, the

FL[4:0] and S[1:0] pins of the FLAG PORT become outputs

and can be connected to the chip which you wish the

GS9021 to write the FLAG data to. In this mode the GS9021

automatically

increments

the

value

S[1:0]

and

subsequently displays the appropriate flags on the FL[4:0]

port, synchronous to the rising edge of PCLKOUT. This is

illustrated in Figure 5d.

Figure 5d displays three properties of the FLAG PORT in

FLAG_MAP mode.

First, each data is present on the FLAG PORT for two clock

cycles to eliminate any setup time violations that might

occur due to clock data skew between chips placed far

apart. However, the designer must still ensure that the hold

time is satisfied. Second, the S[1:0] pins never cycle to the

value of "11" in FLAG_MAP mode since the values

contained in the FL[4:0] register when S[1:0] ="11" are not

considered EDH flags. Also, the chip cycles S[1:0] in the

sequence "01", "00", "10" since this is the order in which the

flags are stored and subsequently decoded from the EDH

packet. Finally the S[1:0] pins only change value after

receipt of an EDH packet and are thus static between

packets. During this inter-packet time, the S[1:0] pins

display a value of "01" and the FL[4:0] pins display the ANC

EDH flags from the preceding EDH packet.

For reliable data output on the FLAG PORT, switching the

FLAG_MAP pin when an EDH packet is exiting the device is

not advised. Also, if the EDH core is bypassed by asserting

the BYPASS_EDH pin HIGH, the flag port will always display

zeros. This is because the incoming flags (which will be

decoded and written to the HOSTIF table) will not be up-

dated to reflect the condition of the input data, and as a

result no outgoing flags will be generated (the FLAG PORT

only displays the outgoing EDH flags).

FLAG_MAP mode can be used to write EDH flags to any

chip, the most common use being applicable when the

processing circuitry following the EDH chip corrupts the

EDH packet. In this case, the FLAG_MAP mode can be

used to route the EDH flags from an input EDH chip around

the processing core and write them to an output EDH chip.

In this configuration, the input IC is in FLAG_MAP mode. It

receives the EDH packet, does normal EDH processing and

transfers the new EDH flags to the output IC. The output IC,

which is not in FLAG_MAP mode but is in write mode

(FLAG_MAP and F_R/W stay LOW) receives these flags as

they are written to it by the EDH chip. The output EDH chip

then updates the EDH packet with the new CRC values and

inserts the preserved EDH flags that have been transferred

from the input IC. A diagram of this can be found in Figure

6b.

Because the flags are output as soon as they are decoded,

the maximum processing latency supported between the

two EDH chips is the number of clock cycles in the shortest

field of the standard minus 15 clock cycles.

For example, D1 has one field of 262 x 1716 = 449592

clock cycles, and one field of 263 x 1716 = 451308 clock

cycles. Thus the maximum latency for D1 is 449592 - 15 =

449577 clock cycles.

Any additional latency requires that the flags be delayed

before they can be piped to the output chip. Since writing to

the flag port takes precedence over the HOSTIF writing, if

any of the flags need to be forced at the output EDH chip,

external logic in the routing path must be added.

Alternately, the HOSTIF of the EDH chip can be used to

perform any additional flag masking.

GS9021 Datasheet(PDF) 13 Page - Gennum Corporation

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