PCM1820 datasheet(7/40 Pages) TI

7 / 40 page

7.5 Electrical Characteristics (continued)

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS,

TDM slave mode (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output data sample

word length

Bits

Interchannel isolation

–1-dB full-scale AC-signal input to non

measurement channel

–124

Interchannel gain

mismatch

–6-dB full-scale AC-signal input

0.1

Gain drift

across temperature range 15°C to 35°C

–4.4

ppm/°C

Interchannel phase

mismatch

1-kHz sinusoidal signal

0.02

Degrees

Phase drift

1-kHz sinusoidal signal, across temperature

range 15°C to 35°C

0.0005

Degrees/°

PSRR

Power-supply rejection

ratio

100-mVPP, 1-kHz sinusoidal signal on AVDD,

differential input selected, 0-dB channel gain

102

CMRR

Common-mode

rejection ratio

Differential microphone input selected, 100-mVPP,

1-kHz signal on both pins and measure level at

output

DIGITAL I/O

VIL

Low-level digital input

logic voltage threshold

All digital pins except FMT0, IOVDD 1.8-V

operation

–0.3

0.30 ×

IOVDD

All digital pins except FMT0, IOVDD 3.3-V

operation

–0.3

0.8

FMT0 Pin

–0.3

0.8

VIH

High-level digital input

logic voltage threshold

All digital pins except FMT0, IOVDD 1.8-V

operation

0.7 ×

IOVDD

IOVDD +

0.3

All digital pins except FMT0, IOVDD 3.3-V

operation

2.1

IOVDD +

0.3

FMT0 Pin

2.1

AVDD +

0.3

VOL

Low-level digital output

voltage

All digital pins, IOL = –2 mA, IOVDD 1.8-V

operation

0.45

All digital pins, IOL = –2 mA, IOVDD 3.3-V

operation

0.4

VOH

High-level digital output

voltage

All digital pins, IOH = 2 mA, IOVDD 1.8-V

operation

IOVDD –

0.45

All digital pins, IOH = 2 mA, IOVDD 3.3-V

operation

2.4

IIH

Input logic-high leakage

for digital inputs

All digital pins, input = IOVDD

–5

0.1

µA

IIL

Input logic-low leakage

for digital inputs

All digital pins, input = 0 V

–5

0.1

µA

CIN

Input capacitance for

digital inputs

All digital pins

RPD

Pulldown resistance for

digital I/O pins when

asserted on

kΩ

TYPICAL SUPPLY CURRENT CONSUMPTION

IAVDD

Current consumption

with all Clocks Disabled

AVDD = 3.3 V, internal AREG

TBD

µA

IIOVDD

All external clocks stopped, IOVDD = 3.3 V

TBD

IIOVDD

All external clocks stopped, IOVDD = 1.8 V

TBD

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PCM1820, PCM1821

SBASA61 – DECEMBER 2020

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