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ZSSC3230BC2B Datasheet(PDF) 32 Page - Renesas Technology Corp |
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ZSSC3230BC2B Datasheet(HTML) 32 Page - Renesas Technology Corp |
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32 / 39 page ![]() ZSSC3230 Datasheet © 2019 Integrated Device Technology, Inc. 32 October 15, 2019 NVM Address Word/Bit Range Default Setting Word/Bit Field Name Description 12HEX (Continued) 14 0BIN sensor_leakage Option to enable sensor element’s leakage current compensation (due to sensor element’s parasitic resistance) leakage cancellation leads to loss of dynamic range and decrease of SNR (loss of 1 bit of effective resolution). The following setups are possible: 0 no sensor leakage cancellation; full internal dynamic range; full Vref applied to external sensor 1 sensor leakage cancellation enabled; applied voltage at external sensor of 0.5 Vref (loss of 1 bit of effective resolution) 15 0BIN sensecap_type Selection of applied (external) sensor capacitance: 0 “differential” sensor capacitance between C0 and CC (CC’) pads 1 single ended sensor capacitance between VSS and CC (CC’) pad; applied voltage at external sensor of 0.5 × Vref (loss of 1 bit of effective resolution) Interrupt Level Setup and Post-Calibration (Digital) Offset Calibration 13HEX 15:0 0000HEX TRSH1[15:0] Bits [15:0] of the 24-bit-wide interrupt threshold1, TRSH1. (The MSBs for this threshold are TRSH1[23:16], which are bits [7:0] of register 15HEX.) 14HEX 15:0 0000HEX TRSH2[15:0] Bits [15:0] of the 24-bit-wide interrupt threshold2, TRSH2. (The MSBs for this threshold are TRSH2[23:16], which are bits[15:8] of register 15HEX.) 15HEX 7:0 00HEX TRSH1[23:16] Bits [23:16] of the 24-bit-wide interrupt threshold1, TRSH1. (The LSBs for this threshold are TRSH1[15:0], which are bits[15:0] of register 13HEX.) 15:8 00HEX TRSH2[23:16] Bits [23:16] of the 24-bit-wide interrupt threshold2, TRSH2. (The LSBs for this threshold are TRSH2[15:0], which are bits[15:0] of register 14HEX.) 16HEX 15:0 0000HEX SENS_Shift[15:0] Bits [15:0] of the post-calibration sensor offset shift coefficient SENS_Shift. (The MSBs of SENS_Shift are bits [7:0] of register 18HEX.) 17HEX 15:0 0000HEX T_Shift[15:0] Bits [15:0] of the post-calibration temperature offset shift coefficient T_Shift. (The MSBs of T_Shift are bits [15:8] of register 18HEX.) 18HEX 7:0 00HEX SENS_Shift[23:16] Bits [23:16] of the post-calibration sensor offset shift coefficient SENS_Shift. (The LSBs of SENS_Shift are in register 16HEX.) 15:8 00HEX T_Shift[23:16] Bits [23:16] of the post-calibration temperature offset shift coefficient T_Shift. (The LSBs of T_Shift are in register 17HEX.) |
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