F59D2G81KA datasheet(21/60 Pages) ESMT

21 / 60 page

ESMT

(Preliminary)

F59D2G81KA (2N)

Elite Semiconductor Memory Technology Inc.

Publication Date: Feb. 2020

Revision: 0.1

21/60

Read / Program / Erase Characteristics

(TA = 0 to 70°C, VCC = 1.7V ~ 1.95V)

Parameter

Symbol

Min

Typ

Max

Unit

Data Transfer from Cell to Register

Program Time

tPROG

400

700

Last Page Program Time

tLPROG

800

1400

Dummy Busy Time for Cache Operation

tCBSY

750

Number of Partial Program Cycles in the Same Page

NOP

cycle

Block Erase Time

tBERS

3.5

Dummy Busy Time for Two-Plane Page Program (following 11h)

tDBSY

0.5

Data Cache Busy Time in Write Cache (following11h )

tDCBSYW1

Data Cache Busy Time in Write Cache (following 15h)

tDCBSYW2

700

Note:

Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 1.8V Vcc and

25°C temperature.

tCBSY max. time depends on timing between internal program completion and data-in.

tDCBSYW2 depends on the timing between internal programming time and data in time.

tLPROG = tPROG(last page) + tPROG(last-1 page) – Command load time(last page) – Address load time(last page)-Data load time(last

page)

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