AS4LC2M8S1 datasheet(10/28 Pages) ALSC

10 / 28 page

ALLIANCE SEMICONDUCTOR

7/5/00

AS4LC2M8S1

AS4LC1M16S1

18 A proper power-up initialization sequence (as described on page 10) is needed before proper device operation is ensured. (V DD and VDDQ must be

powered up simultaneously. VSS and VSSQ must be at the same potential.)Two AUTOREFRESH command wake-ups should be repeated any time the tREF

refresh requirement is exceeded.

19 AC characteristics assume tT = 1 ns.

20 In addition to meeting the transition rate specification, the clock and CKE must transit between V IH and VIL (or between VIL and VIH) in a monotonic

manner.

21 Outputs measured at 1.4 V with equivalent load.

22 AC timing and IDD tests have VIL = 0V and VIH = 2.8 V with timing referenced to 1.4V crossover point.

23 IDD specifications are tested after the device is properly initialized.

24 Minimum clock cycles = (minimum time/clock cycle time) rounded up.

Device operation

Command

Pin settings

Description

Power up

The following sequence is recommended prior to normal operation.

Apply power, start clock, and assert CKE and DQM high. All other

signals are NOP.

After power-up, pause for a minimum of 200µs. CKE/DQM =

high; all others NOP.

Precharge both banks.

Perform Mode Register Set command to initialize mode register.

Perform a minimum of 8 auto refresh cycles to stabilize internal

circuitry.

(Steps 4 and 5 may be interchanged.)

Mode register set

CS = RAS = CAS = WE = low;

A0~A11 = opcode

The mode register stores the user selected opcode for the SDRAM

operating modes. The CAS latency, burst length, burst type, test mode

and other vendor specific functions are selected/programmed during

the Mode Register Set command cycle. The default setting of the mode

that the power-up and mode register set cycle be executed prior to

normal SDRAM operation. Refer to the Mode Register Set table and

timing for details.

Device deselect and

no operation

CS = high, or

RAS, CAS, WE = high

The SDRAM performs a “no operation” (NOP) when RAS, CAS, and

WE = high. Since the NOP performs no operation, it may be used as a

wait state in performing normal SDRAM functions. The SDRAM is

deselected when CS is high. CS high disables the command decoder

such that RAS, CAS, WE and address inputs are ignored. Device

deselection is also considered a NOP.

Bank activation

CS = RAS = low; CAS = WE =

high; A0~A10 = row address;

A11 = bank select

The SDRAM is configured with two internal banks. Use the Bank

Activate command to select a row in one of the two idle banks. Initiate

a read or write operation after tRCD(min) from the time of bank

activation.

30 pF

AS4LC2M8S1 Datasheet(PDF) 10 Page - Alliance Semiconductor Corporation

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