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FAM65HR51DS2 Datasheet(PDF) 4 Page - ON Semiconductor |
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FAM65HR51DS2 Datasheet(HTML) 4 Page - ON Semiconductor |
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4 / 12 page  FAM65HR51DS1, FAM65HR51DS2 www.onsemi.com 4 Table 4. ELECTRICAL SPECIFICATIONS (TJ = 25°C, Unless Otherwise Specified) Symbol Parameter Conditions Min Typ Max Unit BVDSS Drain−to−Source Breakdown Voltage ID = 1 mA, VGS = 0 V 650 − − V VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 3.3 mA 3.0 − 5.0 V RDS(ON) Q1 – Q4 MOSFET On Resistance VGS = 10 V, ID = 20 A − 44 51 m W RDS(ON) Q1 – Q4 MOSFET On Resistance VGS = 10 V, ID = 20 A, TJ = 125°C (Note 4) − 79 − m W gFS Forward Transconductance VDS = 20 V, ID = 20 A (Note 4) − 30 − S IGSS Gate−to−Source Leakage Current VGS = ±20 V, VDS = 0 V −100 − +100 nA IDSS Drain−to−Source Leakage Current VDS = 650 V, VGS = 0 V − − 10 mA DYNAMIC CHARACTERISTICS (Note 4) Ciss Input Capacitance VDS = 400 V VGS = 0 V f = 1 MHz − 4864 − pF Coss Output Capacitance − 109 − pF Crss Reverse Transfer Capacitance − 16 − pF Coss(eff) Effective Output Capacitance VDS = 0 to 520 V VGS = 0 V − 652 − pF Rg Gate Resistance f = 1 MHz − 2 − W Qg(tot) Total Gate Charge VDS = 380 V ID = 20 A VGS = 0 to 10 V − 123 − nC Qgs Gate−to−Source Gate Charge − 37.5 − nC Qgd Gate−to−Drain “Miller” Charge − 49 − nC SWITCHING CHARACTERISTICS (Note 4) ton Turn−on Time VDS = 400 V ID = 20 A VGS = 10 V RG = 4.7 W − 87 − ns td(on) Turn−on Delay Time − 47 − ns tr Turn−on Rise Time − 43 − ns toff Turn−off Time − 148 − ns td(off) Turn−off Delay Time − 118 − ns tf Turn−off Fall Time − 29 − ns BODY DIODE CHARACTERISTICS VSD Source−to−Drain Diode Voltage ISD = 20 A, VGS = 0 V − 0.95 − V Trr Reverse Recovery Time VDS = 520 V, ID = 20 A, dI/dt = 100 A/ms (Note 4) − 133 − ns Qrr Reverse Recovery Charge − 669 − nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Defined by design, not subject to production test Table 5. THERMAL RESISTANCE Parameters Min Typ Max Unit RθJC (per chip) Q1~Q4 Thermal Resistance Junction−to−Case (Note 5) − 0.66 0.92 °C/W RθJS (per chip) Q1~Q4 Thermal Resistance Junction−to−Sink (Note 6) − 1.2 − °C/W 5. Test method compliant with MIL STD 883−1012.1, from case temperature under the chip to case temperature measured below the package at the chip center, Cosmetic oxidation and discoloration on the DBC surface allowed 6. Defined by thermal simulation assuming the module is mounted on a 5 mm Al−360 die casting material with 30 um of 1.8 W/mK thermal interface material Table 6. ISOLATION (Isolation resistance at tested voltage from the base plate to control pins or power terminals.) Test Test Conditions Isolation Resistance Unit Leakage @ Isolation Voltage (Hi−Pot) VAC = 5 kV, 60 Hz 100M < W |
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