October 2000

Copyright ©2000 Alliance Semiconductor. All rights reserved.

®

AS6VA25616

10/6/00

ALLIANCE SEMICONDUCTOR

1

2.7V to 3.3V 256K × 16 Intelliwatt™ low-power CMOS SRAM with one chip enable

Features

• AS6VA25616

• Intelliwatt™ active power circuitry

• Industrial and commercial temperature ranges available

• Organization: 262,144 words × 16 bits

• 2.7V to 3.3V at 55 ns

• Low power consumption: ACTIVE

- 132 mW at 3.3V and 55 ns

• Low power consumption: STANDBY

- 66 µW max at 3.3V

• 1.2V data retention

• Equal access and cycle times

• Easy memory expansion with CS, OE inputs

• Smallest footprint packages

- 48-ball FBGA

- 400-mil 44-pin TSOP II

• ESD protection

≥ 2000 volts

• Latch-up current

≥ 200 mA

Logic block diagram

256K × 16

Array

(4,194,304)

OE

CS

WE

Column decoder

A0

A1

A2

A3

A4

A6

A7

A8

A12

A13

Control circuit

I/O1–I/O8

I/O9–I/O16

UB

LB

I/O

buffer

Pin arrangement (top view)

48-CSP Ball-Grid-Array Package

123456

ALB

OE

A0

A1

A2

NC

BI/O9

UB

A3

A4

CS

I/O1

C

I/O10 I/O11

A5

A6

I/O2

I/O3

A7

I/O4

NC

A16

I/O5

F

I/O15 I/O14

A14

A15

I/O6

I/O7

G

I/O16

NC

A12

A13

WE

I/O8

HNC

A8

A9

A10

A11

NC

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

I/O14

I/O13

I/O12

I/O11

I/O10

I/O9

NC

A8

A9

A10

A11

A12

A0

CS

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O8

WE

A17

A16

A15

44-pin 400-mil TSOP II

21

22

A14

A13

UB

LB

I/O16

I/O15

2

A3

3

A2

4

A1

1

A4

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

43

42

41

44

A6

A7

OE

A5

Selection guide

Product

Speed

(ns)

Power Dissipation

Min

(V)

(V)

Max

(V)

Max (mA)

Max (

AS6VA25616

2.7

3.0

3.3

55

2

20