ADF7030

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

VBAT1

CREG1

VBAT2

CREG2

LNAIN1

LNAIN2

DNC

CREG3

DNC

23

24

25

26

27

28

29

30

22

21

VBAT4

VBAT5

MOSI

MISO

SCLK

GPIO6

DNC

GPIO5

GPIO4

ADF7030

TOP VIEW

(Not to Scale)

NOTES

1. DNC = DO NOT CONNECT.

2. CONNECT THE EXPOSED PAD TO GROUND.

CS

RST

Figure 4. Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

RST

External Reset, Active Low.

2

VBAT1

Power Supply Pin 1 to the Internal Regulators.

3

CREG1

Regulator Output 1. Place a 220 nF capacitor between this pin and ground for regulator stability and noise

rejection. Also, place a 1.2 nF capacitor between this pin and the CLF pin.

4

VBAT2

Power Supply Pin 2 to the Internal Regulators.

5

CREG2

Regulator Output 2. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.

6

LNAIN1

LNA Input 1.

7

LNAIN2

LNA Input 2.

8

DNC

Do Not Connect. Do not connect to this pin.

9

CREG3

Regulator Output 3. Connect to the PA choke inductor to provide bias to the PA. Place a 220 nF capacitor between

this pin and ground for regulator stability and noise rejection.

10

DNC

Do Not Connect. Do not connect to this pin.

11

DNC

Do Not Connect. Do not connect to this pin.

12

PAOUT1

Single-Ended PA1 Output.

13

PAOUT2

Single-Ended PA2 Output.

14

VBAT3

Power Supply Pin 3 to the Internal Regulators.

15

CREG4

Regulator Output 4. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.

16

GPIO0

Digital General-Purpose Input/Output (GPIO) Pin 0.

17

GPIO1

Digital GPIO Pin 1.

18

GPIO2

Digital GPIO Pin 2.

19

GPIO3

Digital GPIO Pin 3.

20

DNC

Do Not Connect. Do not connect to this pin.

21

GPIO4

Digital GPIO Pin 4.

22

GPIO5

Digital GPIO Pin 5.

23

VBAT4

Power Supply Pin 4 to the Internal Regulators.

24

VBAT5

Power Supply Pin 5 to the Internal Regulators.

25

MOSI

Serial Port Master Out/Slave In.

26

MISO

Serial Port Master In/Slave Out.

27

SCLK

Serial Port Clock.

28

CS

inadvertently waking the ADF7030 from sleep.

Rev. 0 | Page 10 of 24