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ADMV7310

Data Sheet

Rev. A | Page 26 of 29

GAIN TUNING PROCEDURE

The ADMV7310 features three different mechanisms to control

the total gain of the transmitter. The first mechanism is the

variable gain control of the variable gain control amplifier of the

transmitter. The variable gain control is controlled by the

VGA_CTL12 pin. The voltage control range to achieve maximum

and minimum gain from the VGA is −5 V to −1 V. The second

mechanism for further gain control is to lower the IVGA_VD345 and

IVGA_VD6 current consumption via the VGA_VG345 and

VGA_VG6 pins from the nominal VGA_VG345 + VGA_VG6

voltage to achieve the nominal IVGA_VD12 + IVGA_VD345 + IVGA_VD6

current consumption. The third mechanism is to lower the

IPA_VD1 current consumption via PA_VG1 from the nominal

PA_VG1 voltage to achieve the nominal IPA_VD1 + IPA_VD2 current

consumption.

See Table 5 for additional details as to which gain control

mechanism to use per the desired gain control range required.

The settings detailed in Table 5 are guidelines for a gain control

approach and may need adjustment depending on application

requirements over temperature and frequency.

Follow the gain tuning order to control the gain to achieve the

correct gain level for optimal performance.

Table 5. Recommended Gain Settings

Gain

Tuning

Order

Gain

Reduction

Range (dB)

Gain Tuning

Recommended

Gain Tuning

Voltage Range (V)

Description of Gain Tuning Procedure

0 to 10

VGA_CTL12

−5 to −1

To achieve maximum gain, set VGA_CTL12 to −5 V. To achieve a gain

reduction between 0 dB and 10 dB, adjust VGA_CTL12 between −5 V

and −1 V (−1 V is the typical minimum gain for the VGA). For both of

these conditions, follow the bias procedure in the Theory of Operation

section to bias the ADMV7310 to the normal operating currents.

10 to 25

VGA_VG345 +

VGA_VG6

−2 to 0

To achieve greater than 10 dB to 25 dB gain reduction, adjust VGA_CTL12

between −5 V and −1 V. If further gain reduction is required to achieve

25 dB gain reduction after conducting Gain Tuning Order 1, lower

IVGA_VD345 + IVGA_VD6 by adjusting VGA_VG345 + VGA_VG6 between −2 V

and 0 V to achieve the correct gain level. The total current consumption of

IVGA_VD345 + IVGA_VD6 while adjusting the VGA_VG345 + VGA_VG6 to drop

to 25 mA (nominal IVGA_VD345 + IVGA_VD6 is 200 mA).

25 to 40

PA_VG1

−2 to 0

To achieve greater than 25 dB to 40 dB gain reduction, adjust VGA_CTL12

to −1 V and adjust the total current consumption of IVGA_VD345 + IVGA_VD6

between 200 mA and 25 mA per Gain Tuning Order 2. If further gain

reduction is needed to achieve 40 dB gain reduction after conducting

Gain Tuning Order 2, lower IPA_VD1 by adjusting PA_VG1 between −2 V

and 0 V to achieve the correct gain level. The total current consumption

of IPA_VD1 while adjusting PA_VG1 must not drop below 80 mA (nominal

IPA_VD1 is 400 mA).

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