ADMV7320 datasheet(25/29 Pages) AD

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Data Sheet

ADMV7320

Rev. C | Page 25 of 29

APPLICATIONS INFORMATION

POWER-UP BIAS SEQUENCE

The ADMV7320 functional blocks use active multiple amplifier

and multiplier stages that all use depletion mode

pseudomorphic high electron mobility transistors (pHEMTs).

To ensure transistor damage does not occur, use the following

power-up bias sequence and do not apply RF power to the

device on the LO or IF ports before powering up the device:

Apply −2 V bias to VG_MULT, VG_AMP, VGA_VG12,

VGA_VG345, VGA_VG6, PA_VG1, and PA_VG2.

Apply −1 V bias to VG_MIXER.

Apply between −5 V (minimum attenuation) and −1 V

(maximum attenuation) bias to VGA_CTL12.

Apply 1.5 V bias to VD_MULT.

Apply a 4 V bias to VD_AMP, VGA_VD12, VGA_VD345,

VGA_VD6, PA_VD1, PA_VD2, DET1_REF_BIAS,

DET1_OUT_BIAS, DET2_REF_BIAS and

DET2_OUT_BIAS (see Figure 86).

Adjust VG_AMP between −2 V and 0 V to achieve a total

IVD_AMP current of 175 mA.

Adjust VGA_VG12 between −2 V and 0 V to achieve a

total IVGA_VD12 current of 35 mA.

Adjust VGA_VG345 and VGA_VG6 between −2 V and 0 V

to achieve a total IVGA_VD345 and IVGA_VD6 current of 215 mA.

Adjust PA_VG1 between −2 V and 0 V to achieve a total

IPA_VD1 current of 400 mA.

10. Adjust PA_VG2 between −2 V and 0 V to achieve a total

IPA_VD2 current of 400 mA.

11. Apply a LO input signal on the LO port and adjust

VG_MULT between −2 V and 0 V to achieve a total

IVD_MULT current of 80 mA.

POWER-DOWN BIAS SEQUENCE

To power-down the ADMV7320, take the following steps:

Apply a 0 V bias to VD_MULT, VD_AMP, VGA_VD12,

VGA_VD345, VGA_VD6, PA_VD1, PA_VD2,

DET1_REF_BIAS, DET1_OUT_BIAS, DET2_REF_BIAS,

and DET2_OUT_BIAS supply voltage per application

circuit.

Apply a 0 V bias to VGA_CTL12.

Apply a 0 V bias to VG_MIXER.

Apply a 0 V bias to VG_MULT, VG_AMP, VGA_VG12,

VGA_VG345, VGA_VG6, PA_VG1, and PA_VG2.

LO NULLING

LO nulling is required to achieve optimal overall RF performance,

especially for LO to RF rejection. This nulling is achieved by

applying dc voltages (VDC) between −0.2 V and +0.2 V to the

IF_IN, IF_IP, IF_QN, and IF_QP ports to suppress the 6× LO

signal at the RFOUT port across the RF frequency band by

approximately 40 dBc. To suppress the 6× LO signal at the

RFOUT port, use the following nulling sequence:

Adjust IF_IN VDC between −0.2 V and +0.2 V. Monitor the

6× LO leakage on the RFOUT port. When the desired or

maximum level of suppression is achieved, proceed to

Step 2.

Adjust IF_IP VDC between −0.2 V and +0.2 V. Monitor the

6× LO leakage on the RFOUT port. When the desired or

maximum level of suppression is achieved, proceed to

Step 3.

Adjust IF_QN VDC input between −0.2 V and +0.2 V.

Monitor the 6× LO leakage on the RFOUT port. When the

desired or maximum level of suppression is achieved,

proceed to Step 4.

Adjust IF_QP VDC between −0.2 V and +0.2 V. Monitor

the 6× LO leakage on the RFOUT port. When the desired

or maximum level of suppression is achieved, proceed to

Step 5.

If the desired level of the 6× LO signal on the RFOUT port

is still not achieved, further tune each dc voltage to the

IF_IN, IF_IP, IF_QN, and IF_QP ports by repeating Step 1

through Step 4. The resolution of the voltage changed on

the dc voltage of the inputs must be in the millivolt.

To ensure that the mixer core is not damaged during the

LO nulling, limit each current to IF_IN, IF_IP, IF_QN,

and IF_QP to 3 mA.

LO nulling must be conducted with any change in input

LO frequency, temperature change, or when Gain Tuning

Order 1 is conducted. The level of suppression changes as

those conditions vary.

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