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ADRV9008-2W/PCBZ Datasheet(PDF) 8 Page - Analog Devices |
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ADRV9008-2W/PCBZ Datasheet(HTML) 8 Page - Analog Devices |
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8 / 95 page  ADRV9008-2 Data Sheet Rev. 0 | Page 8 of 95 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Input Impedance 100 Ω Differential (see Figure 266) Isolation Transmitter 1 (Tx1) to Observation Receiver 1 (ORx1) and Transmitter 2 (Tx2) to Observation Receiver 2 (ORx2) 100 dB 75 MHz < f ≤ 600 MHz 65 dB 600 MHz < f ≤ 5300 MHz 55 dB 5300 MHz < f ≤ 6000 MHz Tx1 to ORx 2 and Tx2 to ORx 1 105 dB 75 MHz < f ≤ 600 MHz 65 dB 600 MHz < f ≤ 5300 MHz 55 dB 5300 MHz < f ≤ 6000 MHz LO SYNTHESIZER LO Frequency Step 2.3 Hz 1.5 GHz to 2.8 GHz, 76.8 MHz phase frequency detector (PFD) frequency LO Spur −85 dBc Excludes integer boundary spurs Integrated Phase Noise 2 kHz to 18 MHz 75 MHz LO 0.014 °rms Narrow PLL loop bandwidth (50 kHz) 1900 MHz LO 0.2 °rms Narrow PLL loop bandwidth (50 kHz) 3800 MHz LO 0.36 °rms Wide PLL loop bandwidth (300 kHz) 5900 MHz LO 0.54 °rms Wide PLL loop bandwidth (300 kHz) Spot Phase Noise 75 MHz LO Narrow PLL loop bandwidth 10 kHz Offset −126.5 dBc/Hz 100 kHz Offset −132.8 dBc/Hz 1 MHz Offset −150.1 dBc/Hz 10 MHz Offset −150.7 dBc/Hz 1900 MHz LO Narrow PLL loop bandwidth 100 kHz Offset −100 dBc/Hz 200 kHz Offset −115 dBc/Hz 400 kHz Offset −120 dBc/Hz 600 kHz Offset −129 dBc/Hz 800 kHz Offset −132 dBc/Hz 1.2 MHz Offset −135 dBc/Hz 1.8 MHz Offset −140 dBc/Hz 6 MHz Offset −150 dBc/Hz 10 MHz Offset −153 dBc/Hz 3800 MHz LO Wide PLL loop bandwidth 100 kHz Offset −104 dBc/Hz 1.2 MHz Offset −125 dBc/Hz 10 MHz Offset −145 dBc/Hz 5900 MHz LO Wide PLL loop bandwidth 100 kHz Offset −99 dBc/Hz 1.2 MHz Offset −119.7 dBc/Hz 10 MHz Offset −135.4 dBc/Hz LO PHASE SYNCHRONIZATION Phase Deviation 1.6 ps/°C Change in LO delay per temperature change |
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