MCP6V16 datasheet(21/52 Pages) MICROCHIP

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DS20006204A-page 21

MCP6V16/6U/7/9

4.2.1.3

Input Current Limits

In order to prevent damage and/or improper operation

of these amplifiers, the circuit must limit the currents

into the input pins (see Section 1.1 “Absolute

Maximum

Ratings †”).

This

requirement

independent of the voltage limits discussed previously.

Figure 4-6 shows one approach to protecting these

inputs. The resistors R1 and R2 limit the possible

current in or out of the input pins (and into D1 and D2).

The diode currents will dump onto VDD.

FIGURE 4-6:

Protecting the Analog Inputs

Against High Currents.

It is also possible to connect the diodes to the left of

resistors R1 and R2. In this case, the currents through

the diodes D1 and D2 need to be limited by some other

mechanism. The resistors then serve as in-rush current

limiters; the DC current into the input pins (VIN+ and

VIN–) should be very small.

A significant amount of current can flow out of the

inputs (through the ESD diodes) when the Common-

mode voltage (VCM) is below ground (VSS); see

Figure 2-14.

4.2.2

RAIL-TO-RAIL OUTPUT

The output voltage range of the MCP6V16/6U/7/9

zero-drift op amps is VDD –20mV (minimum) and

VSS + 20 mV (maximum) when RL =10 kΩ is

connected to VDD/2 and VDD = 5.5V. Refer to

Figure 2-16 and Figure 2-17 for more information.

This op amp is designed to drive light loads; use

another amplifier to buffer the output from heavy loads.

4.3

Application Tips

4.3.1

INPUT OFFSET VOLTAGE OVER

TEMPERATURE

Table 1-1 gives both the linear and quadratic

temperature coefficients (TC1 and TC2) of input offset

voltage. The input offset voltage, at any temperature in

the specified range, can be calculated as follows:

EQUATION 4-1:

4.3.2

DC GAIN PLOTS

Figures 2-9 to 2-11 are histograms of the reciprocals

(in units of µV/V) of CMRR, PSRR and AOL,

respectively. They represent the change in input offset

voltage (VOS) with a change in Common-mode input

voltage (VCM), power supply voltage (VDD) and output

voltage (VOUT).

The 1/AOL histogram is centered near 0 µV/V because

the measurements are dominated by the op amp’s

input noise. The negative values shown represent

noise and tester limitations, not unstable behavior.

Production tests make multiple VOS measurements,

which validates an op amp's stability; an unstable part

would show greater VOS variability, or the output would

stick at one of the supply rails.

4.3.3

OFFSET AT POWER UP

When these parts power up, the input offset (VOS)

starts at its uncorrected value (usually less than

±5 mV). Circuits with high DC gain can cause the

output to reach one of the two rails. In this case, the

time to a valid output is delayed by an output overdrive

time (like tODR), in addition to the start-up time (like

tSTR).

It can be simple to avoid this extra start-up time.

Reducing the gain is one method. Adding a capacitor

across the feedback resistor (RF) is another method.

VDD

min(R1,R2)>

VSS –min(V1,V2)

2mA

VOUT

min(R1,R2)>

max(V1,V2)– VDD

2mA

MCP6V1X

VOS TA



VOS TC1TTC2T

Where:

∆T=

TA –25°C

VOS(TA) = input offset voltage at TA

VOS = input offset voltage at +25°C

TC1 = linear temperature coefficient

TC2 = quadratic temperature coefficient

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