MODEL: 47DV

47DV SPECIFICATIONS

ES-9501 Rev.17 Page 12/13

https://www.m-system.co.jp/

BCD OUTPUT TIMING CHART

Request signals (REQ, MAX_REQ, MIN_REQ) from an external

device (e.g. PLC) are required in order to read out BCD data.

All signals in the following charts are in the negative logic

(ON at LOW signal, as factory set).

• Timing Chart for Single Sampling Cycle Data Output

• Output is provided via open collector, enabling wired-OR gate configuration

When one of REQ signals (REQ, MAX_REQ or MIN_REQ) is given and

its width is between 20 and 50 ms, DATA is established and DAV output

is given in approx. 30 ms from the falling edge of the REQ signal.

Read in the data to a PLC at the timing of the DAV output signal.

DAV is turned off in 40 ms. DATA is turned off in 16 ms after that.

When DATA output logic is negative, wired-OR connection is available

for BCD data, POL, OVF, HH, H, P, L and LL signals.

Measured data is output every 64 ms while one of REQ signals (REQ,

MAX_REQ or MIN_REQ) remains ON. For Event trigger modes, the data

value is the same as the display.

• Timing Chart for Continuous Data Output

30 ms

approx.

47Dx

1

PLC

47Dx

2

47Dx

3

30 ms

approx.

40 ms

40 ms

64 ms

*2

*2. Wait for at least 20 ms between DAV turning off and the next REQ signal.

*2

*2

64 ms

24 ms

40 ms

24 ms

16 ms

all data H

all data H

data

all data H

data

data

20 ms or wider (max. 50 ms)

1

2

3

REQ

DAV

REQ 1

REQ 2

REQ 3

DATA

DAV

MAX_REQ

MIN_REQ

REQ

MAX_REQ

MIN_REQ

DATA

DAV

Hi

Lo

Hi

Lo

Hi

Lo

* 1

*1

DATA

*1

*1. DATA includes BCD Output, POL, OVF, HH, H, P, L, LL and RUN.

Hi

Lo

Hi

Lo

Hi

Lo

Hi

Lo

Hi

Lo

Hi

Lo

Hi

Lo

Hi

Lo

REQ 1

REQ 2

REQ 3

VIEWING ANGLE

The display is designed to provide the optimal legibility

when viewed from the angles as shown below.