VITESSE

SEMICONDUCTOR CORPORATION

Datasheet

VSC834

2.5Gb/s 17x17 Crosspoint Switch

with Input Signal Activity (ISA) Monitoring

Page 2

G52247-0, Rev 4.2

02/09/01

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Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Figure 1: Detailed Block Diagram:

Functional Description

Data Paths

All input data must be differential and biased to PECL levels. On-chip terminations are provided, with a

nominal impedance of 50

Ω. All input termination resistors are tied to V

Data outputs are provided through differential current switches with on-chip terminations that produce a

PECL level output swing. The drive level of the output circuit is designed to produce standard PECL levels

when terminated in 50

Ω to 2.0V. Other termination voltages are possible, such as to V

age level of the output swing will be shifted from its nominal value. The common-mode voltage of the output

swing can be adjusted using the VCOM pin. The adjustment range is not calibrated, but typically allows for

about +200mV of adjustment in the output common-mode voltage.

Output channels can be powered off in pairs if fewer than 17 outputs are required. By connecting the VEE

reduced by roughly 200mW.

17x17

Switch Core

A, AN[16:0]

Y, YN[16:0]

Program Memory

17

Control Interface

DATA[4:0], ADDR[5:0]

ALE, CSB, WRB, RDB INTB,

MONCLK, CONFIG