MIC2127A datasheet(29/38 Pages) MICROCHIP

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 2016 Microchip Technology Inc.

DS20005676B-page 29

MIC2127A

6.0

PCB LAYOUT GUIDELINES

PCB layout is critical to achieve reliable, stable and

efficient performance. The following guidelines should

be followed to ensure proper operation of the

MIC2127A converter.

6.1

• The ceramic bypass capacitors, which are con-

nected to the VDD and PVDD pins, must be located

right at the IC. Use wide traces to connect to the

VDD, PVDD and AGND, and PGND pins respectively.

• The signal ground pin (AGND) must be connected

directly to the ground planes.

• Place the IC close to the point-of-load (POL).

• Signal and power grounds should be kept

separate and connected at only one location.

6.2

Input Capacitor

• Place the input ceramic capacitors as closely as

possible to the MOSFETs.

• Place several vias to the ground plane closely to

the input capacitor ground terminal.

6.3

Inductor

• Keep the inductor connection to the switch node

(SW) short.

• Do not route any digital lines underneath or close

to the inductor.

• Keep the switch node (SW) away from the

feedback (FB) pin.

• The SW pin should be connected directly to the

drain of the low-side MOSFET to accurately

sense the voltage across the low-side MOSFET.

6.4

Output Capacitor

• Use a copper plane to connect the output

capacitor ground terminal to the input capacitor

ground terminal.

• The feedback trace should be separate from the

power trace and connected as closely as possible

to the output capacitor. Sensing a long

high-current load trace can degrade the DC load

regulation.

6.5

MOSFETs

• MOSFET gate drive traces must be short and

wide. The ground plane should be the connection

between the MOSFET source and PGND.

• Chose a low-side MOSFET with a high CGS/CGD

ratio and a low internal gate resistance to

minimize the effect of dv/dt inducted turn-on.

• Use a 4.5V VGS rated MOSFET. Its higher gate

threshold voltage is more immune to glitches than

a 2.5V or 3.3V rated MOSFET.

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